Search

Suchin Parihar

Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1418
Issued Applications
1198
Pending Applications
84
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8810438 [patent_doc_number] => 08448105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Clustering and fanout optimizations of asynchronous circuits' [patent_app_type] => utility [patent_app_number] => 12/429772 [patent_app_country] => US [patent_app_date] => 2009-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13236 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12429772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/429772
Clustering and fanout optimizations of asynchronous circuits Apr 23, 2009 Issued
Array ( [id] => 6241420 [patent_doc_number] => 20100269075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'METHOD AND SYSTEM FOR SELECTIVE STRESS ENABLEMENT IN SIMULATION MODELING' [patent_app_type] => utility [patent_app_number] => 12/426342 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7415 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20100269075.pdf [firstpage_image] =>[orig_patent_app_number] => 12426342 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426342
Method and system for selective stress enablement in simulation modeling Apr 19, 2009 Issued
Array ( [id] => 6218118 [patent_doc_number] => 20110138364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'SEMICONDUCTOR VERIFICATION APPARATUS, METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/056092 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12058 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138364.pdf [firstpage_image] =>[orig_patent_app_number] => 13056092 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/056092
Semiconductor verification apparatus, method, and program Apr 19, 2009 Issued
Array ( [id] => 7734864 [patent_doc_number] => 08103997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits' [patent_app_type] => utility [patent_app_number] => 12/426492 [patent_app_country] => US [patent_app_date] => 2009-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6832 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103997.pdf [firstpage_image] =>[orig_patent_app_number] => 12426492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/426492
Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits Apr 19, 2009 Issued
Array ( [id] => 8297456 [patent_doc_number] => 08225256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Method and apparatus for accelerating project start and tape-out' [patent_app_type] => utility [patent_app_number] => 12/423962 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12423962 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423962
Method and apparatus for accelerating project start and tape-out Apr 14, 2009 Issued
Array ( [id] => 8366769 [patent_doc_number] => 08255849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Solver for modeling a multilayered integrated circuit with three-dimensional interconnects' [patent_app_type] => utility [patent_app_number] => 12/423722 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 19813 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 370 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12423722 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423722
Solver for modeling a multilayered integrated circuit with three-dimensional interconnects Apr 13, 2009 Issued
Array ( [id] => 7734861 [patent_doc_number] => 08103996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method and apparatus for thermal analysis of through-silicon via (TSV)' [patent_app_type] => utility [patent_app_number] => 12/416793 [patent_app_country] => US [patent_app_date] => 2009-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 17858 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103996.pdf [firstpage_image] =>[orig_patent_app_number] => 12416793 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416793
Method and apparatus for thermal analysis of through-silicon via (TSV) Mar 31, 2009 Issued
Array ( [id] => 7734892 [patent_doc_number] => 08104012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-24 [patent_title] => 'System and methods for reducing clock power in integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/363721 [patent_app_country] => US [patent_app_date] => 2009-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/104/08104012.pdf [firstpage_image] =>[orig_patent_app_number] => 12363721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/363721
System and methods for reducing clock power in integrated circuits Jan 30, 2009 Issued
Array ( [id] => 6338552 [patent_doc_number] => 20100199233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Uniquely Marking Products And Product Design Data' [patent_app_type] => utility [patent_app_number] => 12/362841 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6631 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199233.pdf [firstpage_image] =>[orig_patent_app_number] => 12362841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/362841
Uniquely Marking Products And Product Design Data Jan 29, 2009 Abandoned
Array ( [id] => 4602967 [patent_doc_number] => 07979812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method and apparatus for correcting assist-feature-printing errors in a layout' [patent_app_type] => utility [patent_app_number] => 12/363352 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5131 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979812.pdf [firstpage_image] =>[orig_patent_app_number] => 12363352 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/363352
Method and apparatus for correcting assist-feature-printing errors in a layout Jan 29, 2009 Issued
Array ( [id] => 97604 [patent_doc_number] => 07739637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-15 [patent_title] => 'Partial good schema for integrated circuits having parallel execution units' [patent_app_type] => utility [patent_app_number] => 12/362541 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/739/07739637.pdf [firstpage_image] =>[orig_patent_app_number] => 12362541 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/362541
Partial good schema for integrated circuits having parallel execution units Jan 29, 2009 Issued
Array ( [id] => 7726418 [patent_doc_number] => 08099698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Verification test failure analysis' [patent_app_type] => utility [patent_app_number] => 12/362672 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4383 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099698.pdf [firstpage_image] =>[orig_patent_app_number] => 12362672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/362672
Verification test failure analysis Jan 29, 2009 Issued
Array ( [id] => 8530731 [patent_doc_number] => 08307315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Methods and apparatuses for circuit design and optimization' [patent_app_type] => utility [patent_app_number] => 12/363212 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 24 [patent_no_of_words] => 9352 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12363212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/363212
Methods and apparatuses for circuit design and optimization Jan 29, 2009 Issued
Array ( [id] => 6338681 [patent_doc_number] => 20100199251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Heuristic Routing For Electronic Device Layout Designs' [patent_app_type] => utility [patent_app_number] => 12/363211 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8025 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199251.pdf [firstpage_image] =>[orig_patent_app_number] => 12363211 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/363211
Heuristic Routing For Electronic Device Layout Designs Jan 29, 2009 Abandoned
Array ( [id] => 8033883 [patent_doc_number] => 08146036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-03-27 [patent_title] => 'Circuit for and method of determining a process corner for a CMOS device' [patent_app_type] => utility [patent_app_number] => 12/361722 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146036.pdf [firstpage_image] =>[orig_patent_app_number] => 12361722 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361722
Circuit for and method of determining a process corner for a CMOS device Jan 28, 2009 Issued
Array ( [id] => 7813516 [patent_doc_number] => 08136054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Compact abbe\'s kernel generation using principal component analysis' [patent_app_type] => utility [patent_app_number] => 12/362311 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/136/08136054.pdf [firstpage_image] =>[orig_patent_app_number] => 12362311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/362311
Compact abbe's kernel generation using principal component analysis Jan 28, 2009 Issued
Array ( [id] => 6480752 [patent_doc_number] => 20100192111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'PERFORMING LOGIC OPTIMIZATION AND STATE-SPACE REDUCTION FOR HYBRID VERIFICATION' [patent_app_type] => utility [patent_app_number] => 12/361282 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7223 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20100192111.pdf [firstpage_image] =>[orig_patent_app_number] => 12361282 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361282
Performing logic optimization and state-space reduction for hybrid verification Jan 27, 2009 Issued
Array ( [id] => 8389158 [patent_doc_number] => 08266568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-11 [patent_title] => 'Power mesh management method' [patent_app_type] => utility [patent_app_number] => 12/359911 [patent_app_country] => US [patent_app_date] => 2009-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3899 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12359911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359911
Power mesh management method Jan 25, 2009 Issued
Array ( [id] => 5381531 [patent_doc_number] => 20090193370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => ' Bondwire Design' [patent_app_type] => utility [patent_app_number] => 12/359131 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6349 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193370.pdf [firstpage_image] =>[orig_patent_app_number] => 12359131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359131
Bondwire design Jan 22, 2009 Issued
Array ( [id] => 6460890 [patent_doc_number] => 20100190277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Power Network Stacked Via Removal For Congestion Reduction' [patent_app_type] => utility [patent_app_number] => 12/359091 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6495 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20100190277.pdf [firstpage_image] =>[orig_patent_app_number] => 12359091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359091
Power network stacked via removal for congestion reduction Jan 22, 2009 Issued
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