Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6389516 [patent_doc_number] => 20100083200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'METHODS, SYSTEM, AND COMPUTER PROGRAM PRODCUT FOR IMPLEMENTING COMPACT MANUFACTURING MODEL IN ELECTRONIC DESIGN AUTOMATION' [patent_app_type] => utility [patent_app_number] => 12/242442 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11849 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083200.pdf [firstpage_image] =>[orig_patent_app_number] => 12242442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242442
Methods, systems, and computer program products for implementing compact manufacturing models in electronic design automation Sep 29, 2008 Issued
Array ( [id] => 6385474 [patent_doc_number] => 20100077368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Method for Bounded Transactional Timing Analysis' [patent_app_type] => utility [patent_app_number] => 12/237482 [patent_app_country] => US [patent_app_date] => 2008-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9156 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20100077368.pdf [firstpage_image] =>[orig_patent_app_number] => 12237482 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/237482
Method for bounded transactional timing analysis Sep 24, 2008 Issued
Array ( [id] => 5393525 [patent_doc_number] => 20090210838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'INTERPOLATION DISTANCE FOR LAYOUT DESING DATA CORRECTION MODEL' [patent_app_type] => utility [patent_app_number] => 12/212642 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6584 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20090210838.pdf [firstpage_image] =>[orig_patent_app_number] => 12212642 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/212642
INTERPOLATION DISTANCE FOR LAYOUT DESING DATA CORRECTION MODEL Sep 16, 2008 Abandoned
Array ( [id] => 7521138 [patent_doc_number] => 07975247 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Method and system for organizing data generated by electronic design automation tools' [patent_app_type] => utility [patent_app_number] => 12/229972 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5090 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975247.pdf [firstpage_image] =>[orig_patent_app_number] => 12229972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/229972
Method and system for organizing data generated by electronic design automation tools Aug 27, 2008 Issued
Array ( [id] => 8235664 [patent_doc_number] => 08201124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-12 [patent_title] => 'System in package and method of creating system in package' [patent_app_type] => utility [patent_app_number] => 12/198878 [patent_app_country] => US [patent_app_date] => 2008-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 10448 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201124.pdf [firstpage_image] =>[orig_patent_app_number] => 12198878 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/198878
System in package and method of creating system in package Aug 25, 2008 Issued
Array ( [id] => 7734824 [patent_doc_number] => 08103978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method for establishing scattering bar rule' [patent_app_type] => utility [patent_app_number] => 12/198121 [patent_app_country] => US [patent_app_date] => 2008-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2287 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103978.pdf [firstpage_image] =>[orig_patent_app_number] => 12198121 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/198121
Method for establishing scattering bar rule Aug 25, 2008 Issued
Array ( [id] => 6619481 [patent_doc_number] => 20100050138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'SYSTEM AND METHODOLOGY FOR DETERMINING LAYOUT-DEPENDENT EFFECTS IN ULSI SIMULATION' [patent_app_type] => utility [patent_app_number] => 12/196471 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5984 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20100050138.pdf [firstpage_image] =>[orig_patent_app_number] => 12196471 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/196471
System and methodology for determining layout-dependent effects in ULSI simulation Aug 21, 2008 Issued
Array ( [id] => 5332896 [patent_doc_number] => 20090113373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Layout design apparatus, layout design method, and computer product' [patent_app_type] => utility [patent_app_number] => 12/230112 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8113 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113373.pdf [firstpage_image] =>[orig_patent_app_number] => 12230112 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/230112
Layout design apparatus, layout design method, and computer product Aug 21, 2008 Issued
Array ( [id] => 4616661 [patent_doc_number] => 07992114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-02 [patent_title] => 'Timing analysis using statistical on-chip variation' [patent_app_type] => utility [patent_app_number] => 12/135031 [patent_app_country] => US [patent_app_date] => 2008-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9717 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/992/07992114.pdf [firstpage_image] =>[orig_patent_app_number] => 12135031 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135031
Timing analysis using statistical on-chip variation Aug 18, 2008 Issued
Array ( [id] => 5565985 [patent_doc_number] => 20090138838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'METHOD AND APPARATUS FOR SUPPORTING DELAY ANALYSIS, AND COMPUTER PRODUCT' [patent_app_type] => utility [patent_app_number] => 12/193431 [patent_app_country] => US [patent_app_date] => 2008-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10503 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138838.pdf [firstpage_image] =>[orig_patent_app_number] => 12193431 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/193431
Method and apparatus for supporting delay analysis, and computer product Aug 17, 2008 Issued
Array ( [id] => 5523284 [patent_doc_number] => 20090031265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'IC DESIGN MODELING ALLOWING DIMENSION-DEPENDENT RULE CHECKING' [patent_app_type] => utility [patent_app_number] => 12/186764 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10519 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031265.pdf [firstpage_image] =>[orig_patent_app_number] => 12186764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186764
IC design modeling allowing dimension-dependent rule checking Aug 5, 2008 Issued
Array ( [id] => 136710 [patent_doc_number] => 07703061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'IC design modeling allowing dimension-dependent rule checking' [patent_app_type] => utility [patent_app_number] => 12/186769 [patent_app_country] => US [patent_app_date] => 2008-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 10532 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/703/07703061.pdf [firstpage_image] =>[orig_patent_app_number] => 12186769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186769
IC design modeling allowing dimension-dependent rule checking Aug 5, 2008 Issued
Array ( [id] => 4447687 [patent_doc_number] => 07930661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-19 [patent_title] => 'Software model for a hybrid stacked field programmable gate array' [patent_app_type] => utility [patent_app_number] => 12/185511 [patent_app_country] => US [patent_app_date] => 2008-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 9283 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930661.pdf [firstpage_image] =>[orig_patent_app_number] => 12185511 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/185511
Software model for a hybrid stacked field programmable gate array Aug 3, 2008 Issued
Array ( [id] => 6558643 [patent_doc_number] => 20100017158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'GENERATING WORST CASE BIT PATTERNS FOR SIMULTANEOUS SWITCHING NOISE (SSN) IN DIGITAL SYSTEMS' [patent_app_type] => utility [patent_app_number] => 12/176811 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4109 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017158.pdf [firstpage_image] =>[orig_patent_app_number] => 12176811 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/176811
GENERATING WORST CASE BIT PATTERNS FOR SIMULTANEOUS SWITCHING NOISE (SSN) IN DIGITAL SYSTEMS Jul 20, 2008 Abandoned
Array ( [id] => 5351692 [patent_doc_number] => 20090007053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Method of Manufacturing Mask for Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/146772 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4532 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007053.pdf [firstpage_image] =>[orig_patent_app_number] => 12146772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/146772
Method of Manufacturing Mask for Semiconductor Device Jun 25, 2008 Abandoned
Array ( [id] => 5351668 [patent_doc_number] => 20090007029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'METHOD FOR DESIGNING DRIVER' [patent_app_type] => utility [patent_app_number] => 12/145311 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3054 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007029.pdf [firstpage_image] =>[orig_patent_app_number] => 12145311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/145311
Method for designing driver Jun 23, 2008 Issued
Array ( [id] => 7734884 [patent_doc_number] => 08104007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method and apparatus for thermal analysis' [patent_app_type] => utility [patent_app_number] => 12/144651 [patent_app_country] => US [patent_app_date] => 2008-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 11870 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/104/08104007.pdf [firstpage_image] =>[orig_patent_app_number] => 12144651 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144651
Method and apparatus for thermal analysis Jun 23, 2008 Issued
Array ( [id] => 5523287 [patent_doc_number] => 20090031268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'METHODS FOR CHARACTERIZATION OF ELECTRONIC CIRCUITS UNDER PROCESS VARIABILITY EFFECTS' [patent_app_type] => utility [patent_app_number] => 12/144491 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 18575 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031268.pdf [firstpage_image] =>[orig_patent_app_number] => 12144491 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/144491
Methods for characterization of electronic circuits under process variability effects Jun 22, 2008 Issued
Array ( [id] => 4841722 [patent_doc_number] => 20080282208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Integrated Circuit Having Anti-counterfeiting Measures' [patent_app_type] => utility [patent_app_number] => 12/139632 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3851 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20080282208.pdf [firstpage_image] =>[orig_patent_app_number] => 12139632 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/139632
Integrated Circuit Having Anti-counterfeiting Measures Jun 15, 2008 Abandoned
Array ( [id] => 7734870 [patent_doc_number] => 08103999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-24 [patent_title] => 'Debugging of counterexamples in formal verification' [patent_app_type] => utility [patent_app_number] => 12/140172 [patent_app_country] => US [patent_app_date] => 2008-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7890 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103999.pdf [firstpage_image] =>[orig_patent_app_number] => 12140172 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/140172
Debugging of counterexamples in formal verification Jun 15, 2008 Issued
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