Search

Suchin Parihar

Examiner (ID: 11815, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2872, 2851
Total Applications
1384
Issued Applications
1166
Pending Applications
107
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5351679 [patent_doc_number] => 20090007040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'APPARATUS FOR ANALYZING POST-LAYOUT TIMING CRITICAL PATHS' [patent_app_type] => utility [patent_app_number] => 12/139358 [patent_app_country] => US [patent_app_date] => 2008-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6847 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007040.pdf [firstpage_image] =>[orig_patent_app_number] => 12139358 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/139358
Apparatus for analyzing post-layout timing critical paths Jun 12, 2008 Issued
Array ( [id] => 4499534 [patent_doc_number] => 07886237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Method of generating a functional design structure' [patent_app_type] => utility [patent_app_number] => 12/135231 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3286 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886237.pdf [firstpage_image] =>[orig_patent_app_number] => 12135231 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135231
Method of generating a functional design structure Jun 8, 2008 Issued
Array ( [id] => 19186 [patent_doc_number] => 07810060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-05 [patent_title] => 'Critical area computation of composite fault mechanisms using Voronoi diagrams' [patent_app_type] => utility [patent_app_number] => 12/132714 [patent_app_country] => US [patent_app_date] => 2008-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4163 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/810/07810060.pdf [firstpage_image] =>[orig_patent_app_number] => 12132714 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/132714
Critical area computation of composite fault mechanisms using Voronoi diagrams Jun 3, 2008 Issued
Array ( [id] => 8438326 [patent_doc_number] => 08286111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Thermal simulation using adaptive 3D and hierarchical grid mechanisms' [patent_app_type] => utility [patent_app_number] => 12/131821 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18828 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12131821 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131821
Thermal simulation using adaptive 3D and hierarchical grid mechanisms Jun 1, 2008 Issued
Array ( [id] => 7734854 [patent_doc_number] => 08103993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Structure for dynamically allocating lanes to a plurality of PCI express connectors' [patent_app_type] => utility [patent_app_number] => 12/131291 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9631 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103993.pdf [firstpage_image] =>[orig_patent_app_number] => 12131291 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131291
Structure for dynamically allocating lanes to a plurality of PCI express connectors Jun 1, 2008 Issued
Array ( [id] => 4550766 [patent_doc_number] => 07926010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Method of determining defects in photomask' [patent_app_type] => utility [patent_app_number] => 12/131582 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5277 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/926/07926010.pdf [firstpage_image] =>[orig_patent_app_number] => 12131582 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131582
Method of determining defects in photomask Jun 1, 2008 Issued
Array ( [id] => 5305920 [patent_doc_number] => 20090300572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Method of Correcting Etch and Lithographic Processes' [patent_app_type] => utility [patent_app_number] => 12/130741 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3151 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300572.pdf [firstpage_image] =>[orig_patent_app_number] => 12130741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130741
Method of Correcting Etch and Lithographic Processes May 29, 2008 Abandoned
Array ( [id] => 5587506 [patent_doc_number] => 20090106708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'Structure for Reduced Area Active Above-Ground and Below-Supply Noise Suppression Circuits' [patent_app_type] => utility [patent_app_number] => 12/129532 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106708.pdf [firstpage_image] =>[orig_patent_app_number] => 12129532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129532
Structure for reduced area active above-ground and below-supply noise suppression circuits May 28, 2008 Issued
Array ( [id] => 8235650 [patent_doc_number] => 08201112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Structure for managing voltage swings across field effect transistors' [patent_app_type] => utility [patent_app_number] => 12/129522 [patent_app_country] => US [patent_app_date] => 2008-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201112.pdf [firstpage_image] =>[orig_patent_app_number] => 12129522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/129522
Structure for managing voltage swings across field effect transistors May 28, 2008 Issued
Array ( [id] => 8235659 [patent_doc_number] => 08201121 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-12 [patent_title] => 'Early estimation of power consumption for electronic circuit designs' [patent_app_type] => utility [patent_app_number] => 12/128602 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8509 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201121.pdf [firstpage_image] =>[orig_patent_app_number] => 12128602 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/128602
Early estimation of power consumption for electronic circuit designs May 27, 2008 Issued
Array ( [id] => 4528400 [patent_doc_number] => 07934180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Incremental speculative merging' [patent_app_type] => utility [patent_app_number] => 12/127051 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6851 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934180.pdf [firstpage_image] =>[orig_patent_app_number] => 12127051 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127051
Incremental speculative merging May 26, 2008 Issued
Array ( [id] => 4499639 [patent_doc_number] => 07886254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Method for amending layout patterns' [patent_app_type] => utility [patent_app_number] => 12/127801 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4508 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886254.pdf [firstpage_image] =>[orig_patent_app_number] => 12127801 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127801
Method for amending layout patterns May 26, 2008 Issued
Array ( [id] => 5305913 [patent_doc_number] => 20090300565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'METHOD FOR PRIORITIZING NODES FOR REROUTING AND DEVICE THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/127392 [patent_app_country] => US [patent_app_date] => 2008-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20090300565.pdf [firstpage_image] =>[orig_patent_app_number] => 12127392 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127392
Method for prioritizing nodes for rerouting and device therefor May 26, 2008 Issued
Array ( [id] => 4794089 [patent_doc_number] => 20080295063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Method and apparatus for determining factors for design consideration in yield analysis' [patent_app_type] => utility [patent_app_number] => 12/154586 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8722 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20080295063.pdf [firstpage_image] =>[orig_patent_app_number] => 12154586 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/154586
Method and apparatus for determining factors for design consideration in yield analysis May 21, 2008 Issued
Array ( [id] => 5489330 [patent_doc_number] => 20090290401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-26 [patent_title] => 'PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS' [patent_app_type] => utility [patent_app_number] => 12/124472 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6823 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20090290401.pdf [firstpage_image] =>[orig_patent_app_number] => 12124472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124472
Placement and optimization of process dummy cells May 20, 2008 Issued
Array ( [id] => 4462781 [patent_doc_number] => 07895551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Generation of standard cell library components with increased signal routing resources' [patent_app_type] => utility [patent_app_number] => 12/124162 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7752 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895551.pdf [firstpage_image] =>[orig_patent_app_number] => 12124162 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124162
Generation of standard cell library components with increased signal routing resources May 20, 2008 Issued
Array ( [id] => 4678405 [patent_doc_number] => 20080216036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'SLACK SENSITIVITY TO PARAMETER VARIATION BASED TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 12/122451 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216036.pdf [firstpage_image] =>[orig_patent_app_number] => 12122451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/122451
Slack sensitivity to parameter variation based timing analysis May 15, 2008 Issued
Array ( [id] => 8033903 [patent_doc_number] => 08146046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Structures for semiconductor structures with error detection and correction' [patent_app_type] => utility [patent_app_number] => 12/120701 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/146/08146046.pdf [firstpage_image] =>[orig_patent_app_number] => 12120701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/120701
Structures for semiconductor structures with error detection and correction May 14, 2008 Issued
Array ( [id] => 4560459 [patent_doc_number] => 07877724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Decision tree representation of a function' [patent_app_type] => utility [patent_app_number] => 12/117851 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4798 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877724.pdf [firstpage_image] =>[orig_patent_app_number] => 12117851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117851
Decision tree representation of a function May 8, 2008 Issued
Array ( [id] => 5317782 [patent_doc_number] => 20090282380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYSILICON PERIMETER DENSITIES OF INDIVIDUAL CELLS' [patent_app_type] => utility [patent_app_number] => 12/117761 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282380.pdf [firstpage_image] =>[orig_patent_app_number] => 12117761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117761
Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells May 8, 2008 Issued
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