Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4560459 [patent_doc_number] => 07877724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Decision tree representation of a function' [patent_app_type] => utility [patent_app_number] => 12/117851 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4798 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877724.pdf [firstpage_image] =>[orig_patent_app_number] => 12117851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117851
Decision tree representation of a function May 8, 2008 Issued
Array ( [id] => 5317709 [patent_doc_number] => 20090282307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'Optimizing test code generation for verification environment' [patent_app_type] => utility [patent_app_number] => 12/117381 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282307.pdf [firstpage_image] =>[orig_patent_app_number] => 12117381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117381
Optimizing test code generation for verification environment May 7, 2008 Issued
Array ( [id] => 4488913 [patent_doc_number] => 07908574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Techniques for use with automated circuit design and simulations' [patent_app_type] => utility [patent_app_number] => 12/117711 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 18163 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908574.pdf [firstpage_image] =>[orig_patent_app_number] => 12117711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117711
Techniques for use with automated circuit design and simulations May 7, 2008 Issued
Array ( [id] => 7734853 [patent_doc_number] => 08103992 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-24 [patent_title] => 'Rapid rerouting based runtime reconfigurable signal probing' [patent_app_type] => utility [patent_app_number] => 12/114572 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7497 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103992.pdf [firstpage_image] =>[orig_patent_app_number] => 12114572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114572
Rapid rerouting based runtime reconfigurable signal probing May 1, 2008 Issued
Array ( [id] => 4730317 [patent_doc_number] => 20080209098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'STRUCTURE FOR PCI-E BASED POS TERMINAL' [patent_app_type] => utility [patent_app_number] => 12/112541 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4324 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209098.pdf [firstpage_image] =>[orig_patent_app_number] => 12112541 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/112541
Structure for PCI-E based POS terminal Apr 29, 2008 Issued
Array ( [id] => 7532704 [patent_doc_number] => 07844938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Data correcting hierarchical integrated circuit layout accommodating compensate for long range critical dimension variation' [patent_app_type] => utility [patent_app_number] => 12/109400 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844938.pdf [firstpage_image] =>[orig_patent_app_number] => 12109400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/109400
Data correcting hierarchical integrated circuit layout accommodating compensate for long range critical dimension variation Apr 24, 2008 Issued
Array ( [id] => 5560178 [patent_doc_number] => 20090271755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'Unified Layer Stack Architecture' [patent_app_type] => utility [patent_app_number] => 12/109501 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271755.pdf [firstpage_image] =>[orig_patent_app_number] => 12109501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/109501
Unified layer stack architecture Apr 24, 2008 Issued
Array ( [id] => 4587334 [patent_doc_number] => 07849428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Formally deriving a minimal clock-gating scheme' [patent_app_type] => utility [patent_app_number] => 12/107940 [patent_app_country] => US [patent_app_date] => 2008-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/849/07849428.pdf [firstpage_image] =>[orig_patent_app_number] => 12107940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107940
Formally deriving a minimal clock-gating scheme Apr 22, 2008 Issued
Array ( [id] => 5497650 [patent_doc_number] => 20090265678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'System and Method of Resistance Based Memory Circuit Parameter Adjustment' [patent_app_type] => utility [patent_app_number] => 12/107252 [patent_app_country] => US [patent_app_date] => 2008-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10191 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265678.pdf [firstpage_image] =>[orig_patent_app_number] => 12107252 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/107252
System and method of resistance based memory circuit parameter adjustment Apr 21, 2008 Issued
Array ( [id] => 4862622 [patent_doc_number] => 20080270956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING APPARATUS, AND RECORDING MEDIUM STORING SEMICONDUCTOR INTEGRATED CIRCUIT DESIGNING SOFTWARE' [patent_app_type] => utility [patent_app_number] => 12/105572 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270956.pdf [firstpage_image] =>[orig_patent_app_number] => 12105572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105572
Semiconductor integrated circuit designing method, semiconductor integrated circuit designing apparatus, and recording medium storing semiconductor integrated circuit designing software Apr 17, 2008 Issued
Array ( [id] => 4684156 [patent_doc_number] => 20080250382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/062922 [patent_app_country] => US [patent_app_date] => 2008-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4671 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250382.pdf [firstpage_image] =>[orig_patent_app_number] => 12062922 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062922
SEMICONDUCTOR DEVICE MANUFACTURING METHOD Apr 3, 2008 Abandoned
Array ( [id] => 4684135 [patent_doc_number] => 20080250361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same' [patent_app_type] => utility [patent_app_number] => 12/080381 [patent_app_country] => US [patent_app_date] => 2008-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13173 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250361.pdf [firstpage_image] =>[orig_patent_app_number] => 12080381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/080381
Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same Apr 1, 2008 Issued
Array ( [id] => 4558627 [patent_doc_number] => 07890913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Wire mapping for programmable logic devices' [patent_app_type] => utility [patent_app_number] => 12/055170 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8018 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890913.pdf [firstpage_image] =>[orig_patent_app_number] => 12055170 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055170
Wire mapping for programmable logic devices Mar 24, 2008 Issued
Array ( [id] => 38562 [patent_doc_number] => 07788609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and apparatus for optimizing an optical proximity correction model' [patent_app_type] => utility [patent_app_number] => 12/054572 [patent_app_country] => US [patent_app_date] => 2008-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6136 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788609.pdf [firstpage_image] =>[orig_patent_app_number] => 12054572 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054572
Method and apparatus for optimizing an optical proximity correction model Mar 24, 2008 Issued
Array ( [id] => 5405760 [patent_doc_number] => 20090241075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'TEST CHIP VALIDATION AND DEVELOPMENT SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/053852 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1867 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20090241075.pdf [firstpage_image] =>[orig_patent_app_number] => 12053852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/053852
TEST CHIP VALIDATION AND DEVELOPMENT SYSTEM Mar 23, 2008 Abandoned
Array ( [id] => 5405758 [patent_doc_number] => 20090241073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Radiation Tolerance by Clock Signal Interleaving' [patent_app_type] => utility [patent_app_number] => 12/051002 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20090241073.pdf [firstpage_image] =>[orig_patent_app_number] => 12051002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051002
Radiation tolerance by clock signal interleaving Mar 18, 2008 Issued
Array ( [id] => 5405767 [patent_doc_number] => 20090241082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'Method and System for Generating an Accurate Physical Realization for an Integrated Circuit Having Incomplete Physical Constraints' [patent_app_type] => utility [patent_app_number] => 12/051440 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20090241082.pdf [firstpage_image] =>[orig_patent_app_number] => 12051440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/051440
Method and System for Generating an Accurate Physical Realization for an Integrated Circuit Having Incomplete Physical Constraints Mar 18, 2008 Abandoned
Array ( [id] => 4558442 [patent_doc_number] => 07890893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Design structure for semiconductor on-chip repair scheme for negative bias temperature instability' [patent_app_type] => utility [patent_app_number] => 12/050990 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4372 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/890/07890893.pdf [firstpage_image] =>[orig_patent_app_number] => 12050990 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050990
Design structure for semiconductor on-chip repair scheme for negative bias temperature instability Mar 18, 2008 Issued
Array ( [id] => 4761358 [patent_doc_number] => 20080313584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Logic verification method' [patent_app_type] => utility [patent_app_number] => 12/076552 [patent_app_country] => US [patent_app_date] => 2008-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6153 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313584.pdf [firstpage_image] =>[orig_patent_app_number] => 12076552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/076552
Logic verification method Mar 18, 2008 Abandoned
Array ( [id] => 5405144 [patent_doc_number] => 20090240459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'INDENTIFYING SEQUENTIAL FUNCTIONAL PATHS FOR IC TESTING METHODS AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/050381 [patent_app_country] => US [patent_app_date] => 2008-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4350 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20090240459.pdf [firstpage_image] =>[orig_patent_app_number] => 12050381 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/050381
Identifying sequential functional paths for IC testing methods and system Mar 17, 2008 Issued
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