Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4755070 [patent_doc_number] => 20080163146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'APPARATUS FOR INTEGRATED INPUT/OUTPUT CIRCUIT AND VERIFICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/049221 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3581 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20080163146.pdf [firstpage_image] =>[orig_patent_app_number] => 12049221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/049221
APPARATUS FOR INTEGRATED INPUT/OUTPUT CIRCUIT AND VERIFICATION METHOD THEREOF Mar 13, 2008 Abandoned
Array ( [id] => 4741996 [patent_doc_number] => 20080235649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, RECORDING MEDIUM, AND MASK MANUACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 12/048532 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17086 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235649.pdf [firstpage_image] =>[orig_patent_app_number] => 12048532 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048532
Method of designing semiconductor integrated circuit, apparatus for designing semiconductor integrated circuit, recording medium, and mask manufacturing method Mar 13, 2008 Issued
Array ( [id] => 4560319 [patent_doc_number] => 07877709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method of placing wires' [patent_app_type] => utility [patent_app_number] => 12/048791 [patent_app_country] => US [patent_app_date] => 2008-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3527 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877709.pdf [firstpage_image] =>[orig_patent_app_number] => 12048791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/048791
Method of placing wires Mar 13, 2008 Issued
Array ( [id] => 4582553 [patent_doc_number] => 07840925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Source specific timing checks on synchronous elements using a static timing analysis engine' [patent_app_type] => utility [patent_app_number] => 12/047502 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840925.pdf [firstpage_image] =>[orig_patent_app_number] => 12047502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047502
Source specific timing checks on synchronous elements using a static timing analysis engine Mar 12, 2008 Issued
Array ( [id] => 9781476 [patent_doc_number] => 08856700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-07 [patent_title] => 'Methods, systems, and apparatus for reliability synthesis' [patent_app_type] => utility [patent_app_number] => 12/047540 [patent_app_country] => US [patent_app_date] => 2008-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4741 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12047540 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047540
Methods, systems, and apparatus for reliability synthesis Mar 12, 2008 Issued
Array ( [id] => 4602969 [patent_doc_number] => 07979814 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Model implementation on GPU' [patent_app_type] => utility [patent_app_number] => 12/047222 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4807 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979814.pdf [firstpage_image] =>[orig_patent_app_number] => 12047222 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/047222
Model implementation on GPU Mar 11, 2008 Issued
Array ( [id] => 4511472 [patent_doc_number] => 07949966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Data verification method, charged particle beam writing apparatus, and computer-readable storage medium with program' [patent_app_type] => utility [patent_app_number] => 12/042712 [patent_app_country] => US [patent_app_date] => 2008-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7151 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949966.pdf [firstpage_image] =>[orig_patent_app_number] => 12042712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/042712
Data verification method, charged particle beam writing apparatus, and computer-readable storage medium with program Mar 4, 2008 Issued
Array ( [id] => 5540970 [patent_doc_number] => 20090222775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'Characterising circuit cell performance variability in response to pertibations in manufacturing process parameters' [patent_app_type] => utility [patent_app_number] => 12/073050 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5073 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20090222775.pdf [firstpage_image] =>[orig_patent_app_number] => 12073050 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073050
Characterising circuit cell performance variability in response to perturbations in manufacturing process parameters Feb 27, 2008 Issued
Array ( [id] => 5512515 [patent_doc_number] => 20090212819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/037421 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212819.pdf [firstpage_image] =>[orig_patent_app_number] => 12037421 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037421
Method and system for changing circuits in an integrated circuit Feb 25, 2008 Issued
Array ( [id] => 5516918 [patent_doc_number] => 20090217225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/036191 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4498 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217225.pdf [firstpage_image] =>[orig_patent_app_number] => 12036191 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036191
MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS Feb 21, 2008 Abandoned
Array ( [id] => 7525085 [patent_doc_number] => 08028255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/035281 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2832 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028255.pdf [firstpage_image] =>[orig_patent_app_number] => 12035281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035281
Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method Feb 20, 2008 Issued
Array ( [id] => 4621765 [patent_doc_number] => 08001496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Control of design automation process' [patent_app_type] => utility [patent_app_number] => 12/034701 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001496.pdf [firstpage_image] =>[orig_patent_app_number] => 12034701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034701
Control of design automation process Feb 20, 2008 Issued
Array ( [id] => 7734866 [patent_doc_number] => 08103998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Verifying non-deterministic behavior of a design under test' [patent_app_type] => utility [patent_app_number] => 12/034161 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5982 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103998.pdf [firstpage_image] =>[orig_patent_app_number] => 12034161 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034161
Verifying non-deterministic behavior of a design under test Feb 19, 2008 Issued
Array ( [id] => 8260132 [patent_doc_number] => 08209647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-26 [patent_title] => 'Extensible verification system' [patent_app_type] => utility [patent_app_number] => 12/034601 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6716 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12034601 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034601
Extensible verification system Feb 19, 2008 Issued
Array ( [id] => 4441446 [patent_doc_number] => 07971162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Verification of spare latch placement in synthesized macros' [patent_app_type] => utility [patent_app_number] => 12/032841 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 994 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971162.pdf [firstpage_image] =>[orig_patent_app_number] => 12032841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032841
Verification of spare latch placement in synthesized macros Feb 17, 2008 Issued
Array ( [id] => 7734878 [patent_doc_number] => 08104004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Logic performance in cyclic structures' [patent_app_type] => utility [patent_app_number] => 12/030531 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6837 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/104/08104004.pdf [firstpage_image] =>[orig_patent_app_number] => 12030531 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030531
Logic performance in cyclic structures Feb 12, 2008 Issued
Array ( [id] => 5529075 [patent_doc_number] => 20090199152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Methods and apparatuses for reducing mura effects in generated patterns' [patent_app_type] => utility [patent_app_number] => 12/068412 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6330 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199152.pdf [firstpage_image] =>[orig_patent_app_number] => 12068412 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/068412
Methods and apparatuses for reducing mura effects in generated patterns Feb 5, 2008 Abandoned
Array ( [id] => 5529061 [patent_doc_number] => 20090199138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information' [patent_app_type] => utility [patent_app_number] => 12/026141 [patent_app_country] => US [patent_app_date] => 2008-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199138.pdf [firstpage_image] =>[orig_patent_app_number] => 12026141 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/026141
Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information Feb 4, 2008 Issued
Array ( [id] => 5529060 [patent_doc_number] => 20090199137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION' [patent_app_type] => utility [patent_app_number] => 12/023512 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12279 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199137.pdf [firstpage_image] =>[orig_patent_app_number] => 12023512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023512
System and method for multi-exposure pattern decomposition Jan 30, 2008 Issued
Array ( [id] => 7734883 [patent_doc_number] => 08104006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method and apparatus for thermal analysis' [patent_app_type] => utility [patent_app_number] => 12/024002 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5386 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/104/08104006.pdf [firstpage_image] =>[orig_patent_app_number] => 12024002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024002
Method and apparatus for thermal analysis Jan 30, 2008 Issued
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