Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5381538 [patent_doc_number] => 20090193377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/022951 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193377.pdf [firstpage_image] =>[orig_patent_app_number] => 12022951 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/022951
Regular local clock buffer placement and latch clustering by iterative optimization Jan 29, 2008 Issued
Array ( [id] => 4678410 [patent_doc_number] => 20080216041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Integrated circuit simulation method considering stress effects' [patent_app_type] => utility [patent_app_number] => 12/019841 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5116 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216041.pdf [firstpage_image] =>[orig_patent_app_number] => 12019841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019841
Integrated circuit simulation method considering stress effects Jan 24, 2008 Abandoned
Array ( [id] => 5356522 [patent_doc_number] => 20090187866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Electrical Parameter Extraction for Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/016661 [patent_app_country] => US [patent_app_date] => 2008-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187866.pdf [firstpage_image] =>[orig_patent_app_number] => 12016661 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/016661
Electrical parameter extraction for integrated circuit design Jan 17, 2008 Issued
Array ( [id] => 4600864 [patent_doc_number] => 07984405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Method and apparatus for determining the timing of an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/972521 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6612 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984405.pdf [firstpage_image] =>[orig_patent_app_number] => 11972521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972521
Method and apparatus for determining the timing of an integrated circuit design Jan 9, 2008 Issued
Array ( [id] => 7686276 [patent_doc_number] => 20090178015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'METHOD AND SYSTEM FOR REDUCING TURN AROUND TIME OF COMPLICATED ENGINEERING CHANGE ORDERS AND ASIC DESIGN REUTILIZATION' [patent_app_type] => utility [patent_app_number] => 11/969551 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4141 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20090178015.pdf [firstpage_image] =>[orig_patent_app_number] => 11969551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969551
METHOD AND SYSTEM FOR REDUCING TURN AROUND TIME OF COMPLICATED ENGINEERING CHANGE ORDERS AND ASIC DESIGN REUTILIZATION Jan 3, 2008 Abandoned
Array ( [id] => 5438035 [patent_doc_number] => 20090172622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'AUTOMATIC BLOCK COMPOSITION TOOL FOR COMPOSING CUSTOM BLOCKS HAVING NON-STANDARD LIBRARY CELLS IN AN INTEGRATED CIRCUIT DESIGN FLOW' [patent_app_type] => utility [patent_app_number] => 11/968311 [patent_app_country] => US [patent_app_date] => 2008-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4574 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172622.pdf [firstpage_image] =>[orig_patent_app_number] => 11968311 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968311
Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow Jan 1, 2008 Issued
Array ( [id] => 7726409 [patent_doc_number] => 08099689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-17 [patent_title] => 'Method and system for a tiling bias design to facilitate efficient design rule checking' [patent_app_type] => utility [patent_app_number] => 12/005018 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2764 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099689.pdf [firstpage_image] =>[orig_patent_app_number] => 12005018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/005018
Method and system for a tiling bias design to facilitate efficient design rule checking Dec 19, 2007 Issued
Array ( [id] => 4917735 [patent_doc_number] => 20080098336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'Compiler and logic circuit design method' [patent_app_type] => utility [patent_app_number] => 11/987817 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 11844 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098336.pdf [firstpage_image] =>[orig_patent_app_number] => 11987817 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987817
Compiler and logic circuit design method Dec 4, 2007 Abandoned
Array ( [id] => 4787879 [patent_doc_number] => 20080141208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Layout method of semiconductor integrated circuit and computer readable storage medium storing layout program thereof' [patent_app_type] => utility [patent_app_number] => 11/987861 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141208.pdf [firstpage_image] =>[orig_patent_app_number] => 11987861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987861
Layout method of semiconductor integrated circuit and computer-readable storage medium storing layout program thereof Dec 4, 2007 Issued
Array ( [id] => 8366766 [patent_doc_number] => 08255844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/987811 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 11638 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11987811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987811
Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method Dec 3, 2007 Issued
Array ( [id] => 8366766 [patent_doc_number] => 08255844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/987811 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 11638 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11987811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987811
Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method Dec 3, 2007 Issued
Array ( [id] => 8366766 [patent_doc_number] => 08255844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/987811 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 11638 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11987811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987811
Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method Dec 3, 2007 Issued
Array ( [id] => 8366766 [patent_doc_number] => 08255844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-28 [patent_title] => 'Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/987811 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 11638 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11987811 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987811
Coordinated-design supporting apparatus, coordinated-design supporting method, computer product, printed-circuit-board manufacturing method, circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method Dec 3, 2007 Issued
Array ( [id] => 7726408 [patent_doc_number] => 08099688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Circuit design' [patent_app_type] => utility [patent_app_number] => 11/985961 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6761 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099688.pdf [firstpage_image] =>[orig_patent_app_number] => 11985961 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/985961
Circuit design Nov 18, 2007 Issued
Array ( [id] => 5411961 [patent_doc_number] => 20090125860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-14 [patent_title] => 'Auto-Routing Small Jog Eliminator' [patent_app_type] => utility [patent_app_number] => 11/939761 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20090125860.pdf [firstpage_image] =>[orig_patent_app_number] => 11939761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939761
Auto-routing small jog eliminator Nov 13, 2007 Issued
Array ( [id] => 7734844 [patent_doc_number] => 08103988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Use of breakouts in printed circuit board designs' [patent_app_type] => utility [patent_app_number] => 11/937411 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9795 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103988.pdf [firstpage_image] =>[orig_patent_app_number] => 11937411 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/937411
Use of breakouts in printed circuit board designs Nov 7, 2007 Issued
Array ( [id] => 7803852 [patent_doc_number] => 08132136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Dynamic critical path detector for digital logic circuit paths' [patent_app_type] => utility [patent_app_number] => 11/937111 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/132/08132136.pdf [firstpage_image] =>[orig_patent_app_number] => 11937111 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/937111
Dynamic critical path detector for digital logic circuit paths Nov 7, 2007 Issued
Array ( [id] => 4528388 [patent_doc_number] => 07934178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Layout method of semiconductor circuit, program and design support system' [patent_app_type] => utility [patent_app_number] => 11/934971 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934178.pdf [firstpage_image] =>[orig_patent_app_number] => 11934971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934971
Layout method of semiconductor circuit, program and design support system Nov 4, 2007 Issued
Array ( [id] => 118465 [patent_doc_number] => 07716616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Slack sensitivity to parameter variation based timing analysis' [patent_app_type] => utility [patent_app_number] => 11/930924 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5222 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716616.pdf [firstpage_image] =>[orig_patent_app_number] => 11930924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/930924
Slack sensitivity to parameter variation based timing analysis Oct 30, 2007 Issued
Array ( [id] => 284232 [patent_doc_number] => 07555735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'IC design modeling allowing dimension-dependent rule checking' [patent_app_type] => utility [patent_app_number] => 11/926289 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 10502 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555735.pdf [firstpage_image] =>[orig_patent_app_number] => 11926289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/926289
IC design modeling allowing dimension-dependent rule checking Oct 28, 2007 Issued
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