Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4966382 [patent_doc_number] => 20080109202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'VERIFICATION AND REACHABILITY USING AN ORGANIC APPROACH' [patent_app_type] => utility [patent_app_number] => 11/924291 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109202.pdf [firstpage_image] =>[orig_patent_app_number] => 11924291 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924291
Verification and reachability using an organic approach Oct 24, 2007 Issued
Array ( [id] => 4963084 [patent_doc_number] => 20080105904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network' [patent_app_type] => utility [patent_app_number] => 11/907320 [patent_app_country] => US [patent_app_date] => 2007-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20080105904.pdf [firstpage_image] =>[orig_patent_app_number] => 11907320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/907320
Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network Oct 10, 2007 Abandoned
Array ( [id] => 4787864 [patent_doc_number] => 20080141193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Properties In Electronic Design Automation' [patent_app_type] => utility [patent_app_number] => 11/869731 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15320 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141193.pdf [firstpage_image] =>[orig_patent_app_number] => 11869731 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869731
Properties In Electronic Design Automation Oct 8, 2007 Abandoned
Array ( [id] => 4693941 [patent_doc_number] => 20080086712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'METHOD OF DESIGNING A PATTERN' [patent_app_type] => utility [patent_app_number] => 11/867841 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3305 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086712.pdf [firstpage_image] =>[orig_patent_app_number] => 11867841 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/867841
Method of designing a pattern Oct 4, 2007 Issued
Array ( [id] => 5442925 [patent_doc_number] => 20090094564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'METHOD FOR RAPID RETURN PATH TRACING' [patent_app_type] => utility [patent_app_number] => 11/866591 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2218 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20090094564.pdf [firstpage_image] =>[orig_patent_app_number] => 11866591 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866591
METHOD FOR RAPID RETURN PATH TRACING Oct 2, 2007 Abandoned
Array ( [id] => 5430411 [patent_doc_number] => 20090089721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 11/866231 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5012 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089721.pdf [firstpage_image] =>[orig_patent_app_number] => 11866231 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866231
METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION Oct 1, 2007 Abandoned
Array ( [id] => 118496 [patent_doc_number] => 07716627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-11 [patent_title] => 'Solution-dependent regularization method for quantizing continuous-tone lithography masks' [patent_app_type] => utility [patent_app_number] => 11/864381 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716627.pdf [firstpage_image] =>[orig_patent_app_number] => 11864381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864381
Solution-dependent regularization method for quantizing continuous-tone lithography masks Sep 27, 2007 Issued
Array ( [id] => 5448193 [patent_doc_number] => 20090049419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/905321 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9887 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20090049419.pdf [firstpage_image] =>[orig_patent_app_number] => 11905321 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/905321
Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method Sep 27, 2007 Issued
Array ( [id] => 7726407 [patent_doc_number] => 08099687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Interchangeable connection arrays for double-sided DIMM placement' [patent_app_type] => utility [patent_app_number] => 11/899497 [patent_app_country] => US [patent_app_date] => 2007-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2624 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099687.pdf [firstpage_image] =>[orig_patent_app_number] => 11899497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/899497
Interchangeable connection arrays for double-sided DIMM placement Sep 4, 2007 Issued
Array ( [id] => 118462 [patent_doc_number] => 07716615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Redundant critical path circuits to meet performance requirement' [patent_app_type] => utility [patent_app_number] => 11/848278 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4351 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716615.pdf [firstpage_image] =>[orig_patent_app_number] => 11848278 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848278
Redundant critical path circuits to meet performance requirement Aug 30, 2007 Issued
Array ( [id] => 58371 [patent_doc_number] => 07774730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Method of and system for designing semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/846948 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6275 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774730.pdf [firstpage_image] =>[orig_patent_app_number] => 11846948 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846948
Method of and system for designing semiconductor integrated circuit Aug 28, 2007 Issued
Array ( [id] => 4590492 [patent_doc_number] => 07831935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Method and architecture for power management of an electronic device' [patent_app_type] => utility [patent_app_number] => 11/846578 [patent_app_country] => US [patent_app_date] => 2007-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4696 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831935.pdf [firstpage_image] =>[orig_patent_app_number] => 11846578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/846578
Method and architecture for power management of an electronic device Aug 28, 2007 Issued
Array ( [id] => 108151 [patent_doc_number] => 07725851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Device, system and method for formal verification' [patent_app_type] => utility [patent_app_number] => 11/845118 [patent_app_country] => US [patent_app_date] => 2007-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6968 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725851.pdf [firstpage_image] =>[orig_patent_app_number] => 11845118 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/845118
Device, system and method for formal verification Aug 26, 2007 Issued
Array ( [id] => 7532702 [patent_doc_number] => 07844936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-30 [patent_title] => 'Method of making an integrated circuit having fill structures' [patent_app_type] => utility [patent_app_number] => 11/843270 [patent_app_country] => US [patent_app_date] => 2007-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4476 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/844/07844936.pdf [firstpage_image] =>[orig_patent_app_number] => 11843270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/843270
Method of making an integrated circuit having fill structures Aug 21, 2007 Issued
Array ( [id] => 4499565 [patent_doc_number] => 07886242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-08 [patent_title] => 'Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs' [patent_app_type] => utility [patent_app_number] => 11/842820 [patent_app_country] => US [patent_app_date] => 2007-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6674 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886242.pdf [firstpage_image] =>[orig_patent_app_number] => 11842820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842820
Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs Aug 20, 2007 Issued
Array ( [id] => 5298381 [patent_doc_number] => 20090013307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'MULTI-RATE HIERARCHICAL STATE DIAGRAMS' [patent_app_type] => utility [patent_app_number] => 11/842014 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16836 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013307.pdf [firstpage_image] =>[orig_patent_app_number] => 11842014 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842014
Multi-rate hierarchical state diagrams Aug 19, 2007 Issued
Array ( [id] => 4508923 [patent_doc_number] => 07958467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Deterministic system and method for generating wiring layouts for integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/840050 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6129 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958467.pdf [firstpage_image] =>[orig_patent_app_number] => 11840050 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840050
Deterministic system and method for generating wiring layouts for integrated circuits Aug 15, 2007 Issued
Array ( [id] => 7734820 [patent_doc_number] => 08103976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Photo mask set for forming multi-layered interconnection lines and semiconductor device fabricated using the same' [patent_app_type] => utility [patent_app_number] => 11/839478 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 5769 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103976.pdf [firstpage_image] =>[orig_patent_app_number] => 11839478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/839478
Photo mask set for forming multi-layered interconnection lines and semiconductor device fabricated using the same Aug 14, 2007 Issued
Array ( [id] => 7726420 [patent_doc_number] => 08099700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-17 [patent_title] => 'Automatic integrated circuit routing using spines' [patent_app_type] => utility [patent_app_number] => 11/838726 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 9497 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099700.pdf [firstpage_image] =>[orig_patent_app_number] => 11838726 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838726
Automatic integrated circuit routing using spines Aug 13, 2007 Issued
Array ( [id] => 27575 [patent_doc_number] => 07802208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-21 [patent_title] => 'Design automation using spine routing' [patent_app_type] => utility [patent_app_number] => 11/838704 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 9499 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802208.pdf [firstpage_image] =>[orig_patent_app_number] => 11838704 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838704
Design automation using spine routing Aug 13, 2007 Issued
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