Search

Suchin Parihar

Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1418
Issued Applications
1198
Pending Applications
84
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5540970 [patent_doc_number] => 20090222775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-03 [patent_title] => 'Characterising circuit cell performance variability in response to pertibations in manufacturing process parameters' [patent_app_type] => utility [patent_app_number] => 12/073050 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5073 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20090222775.pdf [firstpage_image] =>[orig_patent_app_number] => 12073050 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073050
Characterising circuit cell performance variability in response to perturbations in manufacturing process parameters Feb 27, 2008 Issued
Array ( [id] => 5512515 [patent_doc_number] => 20090212819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/037421 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20090212819.pdf [firstpage_image] =>[orig_patent_app_number] => 12037421 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/037421
Method and system for changing circuits in an integrated circuit Feb 25, 2008 Issued
Array ( [id] => 5516918 [patent_doc_number] => 20090217225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/036191 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4498 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217225.pdf [firstpage_image] =>[orig_patent_app_number] => 12036191 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036191
MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS Feb 21, 2008 Abandoned
Array ( [id] => 4621765 [patent_doc_number] => 08001496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-16 [patent_title] => 'Control of design automation process' [patent_app_type] => utility [patent_app_number] => 12/034701 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001496.pdf [firstpage_image] =>[orig_patent_app_number] => 12034701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034701
Control of design automation process Feb 20, 2008 Issued
Array ( [id] => 7525085 [patent_doc_number] => 08028255 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/035281 [patent_app_country] => US [patent_app_date] => 2008-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2832 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028255.pdf [firstpage_image] =>[orig_patent_app_number] => 12035281 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/035281
Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method Feb 20, 2008 Issued
Array ( [id] => 7734866 [patent_doc_number] => 08103998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Verifying non-deterministic behavior of a design under test' [patent_app_type] => utility [patent_app_number] => 12/034161 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5982 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103998.pdf [firstpage_image] =>[orig_patent_app_number] => 12034161 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034161
Verifying non-deterministic behavior of a design under test Feb 19, 2008 Issued
Array ( [id] => 8260132 [patent_doc_number] => 08209647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-26 [patent_title] => 'Extensible verification system' [patent_app_type] => utility [patent_app_number] => 12/034601 [patent_app_country] => US [patent_app_date] => 2008-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6716 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12034601 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/034601
Extensible verification system Feb 19, 2008 Issued
Array ( [id] => 4441446 [patent_doc_number] => 07971162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Verification of spare latch placement in synthesized macros' [patent_app_type] => utility [patent_app_number] => 12/032841 [patent_app_country] => US [patent_app_date] => 2008-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 994 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/971/07971162.pdf [firstpage_image] =>[orig_patent_app_number] => 12032841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/032841
Verification of spare latch placement in synthesized macros Feb 17, 2008 Issued
Array ( [id] => 7734878 [patent_doc_number] => 08104004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Logic performance in cyclic structures' [patent_app_type] => utility [patent_app_number] => 12/030531 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6837 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/104/08104004.pdf [firstpage_image] =>[orig_patent_app_number] => 12030531 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/030531
Logic performance in cyclic structures Feb 12, 2008 Issued
Array ( [id] => 5529075 [patent_doc_number] => 20090199152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Methods and apparatuses for reducing mura effects in generated patterns' [patent_app_type] => utility [patent_app_number] => 12/068412 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6330 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199152.pdf [firstpage_image] =>[orig_patent_app_number] => 12068412 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/068412
Methods and apparatuses for reducing mura effects in generated patterns Feb 5, 2008 Abandoned
Array ( [id] => 5529061 [patent_doc_number] => 20090199138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information' [patent_app_type] => utility [patent_app_number] => 12/026141 [patent_app_country] => US [patent_app_date] => 2008-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199138.pdf [firstpage_image] =>[orig_patent_app_number] => 12026141 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/026141
Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information Feb 4, 2008 Issued
Array ( [id] => 5529060 [patent_doc_number] => 20090199137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION' [patent_app_type] => utility [patent_app_number] => 12/023512 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12279 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20090199137.pdf [firstpage_image] =>[orig_patent_app_number] => 12023512 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/023512
System and method for multi-exposure pattern decomposition Jan 30, 2008 Issued
Array ( [id] => 7734883 [patent_doc_number] => 08104006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method and apparatus for thermal analysis' [patent_app_type] => utility [patent_app_number] => 12/024002 [patent_app_country] => US [patent_app_date] => 2008-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5386 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/104/08104006.pdf [firstpage_image] =>[orig_patent_app_number] => 12024002 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/024002
Method and apparatus for thermal analysis Jan 30, 2008 Issued
Array ( [id] => 5381538 [patent_doc_number] => 20090193377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/022951 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193377.pdf [firstpage_image] =>[orig_patent_app_number] => 12022951 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/022951
Regular local clock buffer placement and latch clustering by iterative optimization Jan 29, 2008 Issued
Array ( [id] => 4678410 [patent_doc_number] => 20080216041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Integrated circuit simulation method considering stress effects' [patent_app_type] => utility [patent_app_number] => 12/019841 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5116 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216041.pdf [firstpage_image] =>[orig_patent_app_number] => 12019841 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019841
Integrated circuit simulation method considering stress effects Jan 24, 2008 Abandoned
Array ( [id] => 5356522 [patent_doc_number] => 20090187866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'Electrical Parameter Extraction for Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/016661 [patent_app_country] => US [patent_app_date] => 2008-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187866.pdf [firstpage_image] =>[orig_patent_app_number] => 12016661 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/016661
Electrical parameter extraction for integrated circuit design Jan 17, 2008 Issued
Array ( [id] => 4600864 [patent_doc_number] => 07984405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Method and apparatus for determining the timing of an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/972521 [patent_app_country] => US [patent_app_date] => 2008-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6612 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984405.pdf [firstpage_image] =>[orig_patent_app_number] => 11972521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/972521
Method and apparatus for determining the timing of an integrated circuit design Jan 9, 2008 Issued
Array ( [id] => 7686276 [patent_doc_number] => 20090178015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'METHOD AND SYSTEM FOR REDUCING TURN AROUND TIME OF COMPLICATED ENGINEERING CHANGE ORDERS AND ASIC DESIGN REUTILIZATION' [patent_app_type] => utility [patent_app_number] => 11/969551 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4141 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20090178015.pdf [firstpage_image] =>[orig_patent_app_number] => 11969551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969551
METHOD AND SYSTEM FOR REDUCING TURN AROUND TIME OF COMPLICATED ENGINEERING CHANGE ORDERS AND ASIC DESIGN REUTILIZATION Jan 3, 2008 Abandoned
Array ( [id] => 5438035 [patent_doc_number] => 20090172622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'AUTOMATIC BLOCK COMPOSITION TOOL FOR COMPOSING CUSTOM BLOCKS HAVING NON-STANDARD LIBRARY CELLS IN AN INTEGRATED CIRCUIT DESIGN FLOW' [patent_app_type] => utility [patent_app_number] => 11/968311 [patent_app_country] => US [patent_app_date] => 2008-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4574 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172622.pdf [firstpage_image] =>[orig_patent_app_number] => 11968311 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/968311
Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow Jan 1, 2008 Issued
Array ( [id] => 7726409 [patent_doc_number] => 08099689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-17 [patent_title] => 'Method and system for a tiling bias design to facilitate efficient design rule checking' [patent_app_type] => utility [patent_app_number] => 12/005018 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2764 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/099/08099689.pdf [firstpage_image] =>[orig_patent_app_number] => 12005018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/005018
Method and system for a tiling bias design to facilitate efficient design rule checking Dec 19, 2007 Issued
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