
Suchin Parihar
Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2872 |
| Total Applications | 1418 |
| Issued Applications | 1198 |
| Pending Applications | 84 |
| Abandoned Applications | 154 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5540970
[patent_doc_number] => 20090222775
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[patent_kind] => A1
[patent_issue_date] => 2009-09-03
[patent_title] => 'Characterising circuit cell performance variability in response to pertibations in manufacturing process parameters'
[patent_app_type] => utility
[patent_app_number] => 12/073050
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/073050 | Characterising circuit cell performance variability in response to perturbations in manufacturing process parameters | Feb 27, 2008 | Issued |
Array
(
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[patent_doc_number] => 20090212819
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[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT'
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[firstpage_image] =>[orig_patent_app_number] => 12037421
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/037421 | Method and system for changing circuits in an integrated circuit | Feb 25, 2008 | Issued |
Array
(
[id] => 5516918
[patent_doc_number] => 20090217225
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS'
[patent_app_type] => utility
[patent_app_number] => 12/036191
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/036191 | MULTI-MODE MULTI-CORNER CLOCKTREE SYNTHESIS | Feb 21, 2008 | Abandoned |
Array
(
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[patent_issue_date] => 2011-08-16
[patent_title] => 'Control of design automation process'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/034701 | Control of design automation process | Feb 20, 2008 | Issued |
Array
(
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[patent_title] => 'Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/035281 | Semiconductor integrated circuit, semiconductor integrated circuit design support device, and semiconductor integrated circuit manufacturing method | Feb 20, 2008 | Issued |
Array
(
[id] => 7734866
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[patent_title] => 'Verifying non-deterministic behavior of a design under test'
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Array
(
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[patent_title] => 'Extensible verification system'
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Array
(
[id] => 4441446
[patent_doc_number] => 07971162
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[patent_issue_date] => 2011-06-28
[patent_title] => 'Verification of spare latch placement in synthesized macros'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/032841 | Verification of spare latch placement in synthesized macros | Feb 17, 2008 | Issued |
Array
(
[id] => 7734878
[patent_doc_number] => 08104004
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[patent_issue_date] => 2012-01-24
[patent_title] => 'Logic performance in cyclic structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/030531 | Logic performance in cyclic structures | Feb 12, 2008 | Issued |
Array
(
[id] => 5529075
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[patent_issue_date] => 2009-08-06
[patent_title] => 'Methods and apparatuses for reducing mura effects in generated patterns'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/068412 | Methods and apparatuses for reducing mura effects in generated patterns | Feb 5, 2008 | Abandoned |
Array
(
[id] => 5529061
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[patent_title] => 'Method and Apparatus for Evaluating Integrated Circuit Design Model Performance Using Basic Block Vectors and Fly-By Vectors Including Microarchitecture Dependent Information'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026141 | Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information | Feb 4, 2008 | Issued |
Array
(
[id] => 5529060
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[patent_title] => 'SYSTEM AND METHOD FOR MULTI-EXPOSURE PATTERN DECOMPOSITION'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/023512 | System and method for multi-exposure pattern decomposition | Jan 30, 2008 | Issued |
Array
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Array
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[patent_title] => 'REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION'
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Array
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/968311 | Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow | Jan 1, 2008 | Issued |
Array
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