Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4592931 [patent_doc_number] => 07853907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Over approximation of integrated circuit based clock gating logic' [patent_app_type] => utility [patent_app_number] => 11/836160 [patent_app_country] => US [patent_app_date] => 2007-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853907.pdf [firstpage_image] =>[orig_patent_app_number] => 11836160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/836160
Over approximation of integrated circuit based clock gating logic Aug 8, 2007 Issued
Array ( [id] => 5363056 [patent_doc_number] => 20090037850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS' [patent_app_type] => utility [patent_app_number] => 11/831990 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4272 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037850.pdf [firstpage_image] =>[orig_patent_app_number] => 11831990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831990
POLYGONAL AREA DESIGN RULE CORRECTION METHOD FOR VLSI LAYOUTS Jul 31, 2007 Abandoned
Array ( [id] => 5358604 [patent_doc_number] => 20090033398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Clock Distribution Network Wiring Structure' [patent_app_type] => utility [patent_app_number] => 11/830910 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5826 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20090033398.pdf [firstpage_image] =>[orig_patent_app_number] => 11830910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830910
Clock distribution network wiring structure Jul 30, 2007 Issued
Array ( [id] => 4455152 [patent_doc_number] => 07966587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Information storage medium on which is stored an interconnection program, interconnection method, interconnection apparatus, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/798981 [patent_app_country] => US [patent_app_date] => 2007-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5705 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966587.pdf [firstpage_image] =>[orig_patent_app_number] => 11798981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/798981
Information storage medium on which is stored an interconnection program, interconnection method, interconnection apparatus, and semiconductor device May 17, 2007 Issued
Array ( [id] => 108177 [patent_doc_number] => 07725872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Orientation dependent shielding for use with dipole illumination techniques' [patent_app_type] => utility [patent_app_number] => 11/797407 [patent_app_country] => US [patent_app_date] => 2007-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 7806 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725872.pdf [firstpage_image] =>[orig_patent_app_number] => 11797407 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/797407
Orientation dependent shielding for use with dipole illumination techniques May 2, 2007 Issued
Array ( [id] => 333378 [patent_doc_number] => 07512915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Embedded test circuit for testing integrated circuits at the die level' [patent_app_type] => utility [patent_app_number] => 11/739819 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4925 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512915.pdf [firstpage_image] =>[orig_patent_app_number] => 11739819 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/739819
Embedded test circuit for testing integrated circuits at the die level Apr 24, 2007 Issued
Array ( [id] => 4590133 [patent_doc_number] => 07861191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Method and apparatus for characterizing signals' [patent_app_type] => utility [patent_app_number] => 11/740209 [patent_app_country] => US [patent_app_date] => 2007-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7136 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861191.pdf [firstpage_image] =>[orig_patent_app_number] => 11740209 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/740209
Method and apparatus for characterizing signals Apr 24, 2007 Issued
Array ( [id] => 5226775 [patent_doc_number] => 20070256042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'METHOD AND SYSTEM FOR INCORPORATING VIA REDUNDANCY IN TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 11/737759 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3494 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20070256042.pdf [firstpage_image] =>[orig_patent_app_number] => 11737759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/737759
Method and system for incorporating via redundancy in timing analysis Apr 19, 2007 Issued
Array ( [id] => 8087789 [patent_doc_number] => 08151229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-03 [patent_title] => 'System and method of computing pin criticalities under process variations for timing analysis and optimization' [patent_app_type] => utility [patent_app_number] => 11/733749 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6256 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151229.pdf [firstpage_image] =>[orig_patent_app_number] => 11733749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733749
System and method of computing pin criticalities under process variations for timing analysis and optimization Apr 9, 2007 Issued
Array ( [id] => 5161764 [patent_doc_number] => 20070174808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method and apparatus for determining a process model that uses feature detection' [patent_app_type] => utility [patent_app_number] => 11/728089 [patent_app_country] => US [patent_app_date] => 2007-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174808.pdf [firstpage_image] =>[orig_patent_app_number] => 11728089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/728089
Method and apparatus for determining a process model that uses feature detection Mar 22, 2007 Issued
Array ( [id] => 4472686 [patent_doc_number] => 07937673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-03 [patent_title] => 'Method and system for implementing top down design and verification of an electrical circuit design' [patent_app_type] => utility [patent_app_number] => 11/717589 [patent_app_country] => US [patent_app_date] => 2007-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7973 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937673.pdf [firstpage_image] =>[orig_patent_app_number] => 11717589 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717589
Method and system for implementing top down design and verification of an electrical circuit design Mar 11, 2007 Issued
Array ( [id] => 4700396 [patent_doc_number] => 20080222580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'SYSTEM AND METHOD FOR MANAGING THE DESIGN AND CONFIGURATION OF AN \nINTEGRATED CIRCUIT SEMICONDUCTOR DESIGN' [patent_app_type] => utility [patent_app_number] => 11/684156 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11633 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222580.pdf [firstpage_image] =>[orig_patent_app_number] => 11684156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/684156
System and method for managing the design and configuration of an integrated circuit semiconductor design Mar 8, 2007 Issued
Array ( [id] => 4700405 [patent_doc_number] => 20080222589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Protecting Trade Secrets During the Design and Configuration of an Integrated Circuit Semiconductor Design' [patent_app_type] => utility [patent_app_number] => 11/684205 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11588 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222589.pdf [firstpage_image] =>[orig_patent_app_number] => 11684205 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/684205
Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design Mar 8, 2007 Issued
Array ( [id] => 4699665 [patent_doc_number] => 20080221849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Method, Apparatus And Computer Program Product For Creating Electric Circuit Models Of Semiconductor Circuits From Fabrication Process Parameters' [patent_app_type] => utility [patent_app_number] => 11/684124 [patent_app_country] => US [patent_app_date] => 2007-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4446 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20080221849.pdf [firstpage_image] =>[orig_patent_app_number] => 11684124 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/684124
Method, Apparatus And Computer Program Product For Creating Electric Circuit Models Of Semiconductor Circuits From Fabrication Process Parameters Mar 8, 2007 Abandoned
Array ( [id] => 4700394 [patent_doc_number] => 20080222578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'SYSTEM AND METHOD FOR CIRCUIT DESIGN SCALING' [patent_app_type] => utility [patent_app_number] => 11/683539 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5094 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222578.pdf [firstpage_image] =>[orig_patent_app_number] => 11683539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683539
System and method for circuit design scaling Mar 7, 2007 Issued
Array ( [id] => 4700406 [patent_doc_number] => 20080222590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Method and System for Building Binary Decision Diagrams Optimally for Nodes in a Netlist Graph Using Don\'t-Caring' [patent_app_type] => utility [patent_app_number] => 11/683495 [patent_app_country] => US [patent_app_date] => 2007-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3612 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222590.pdf [firstpage_image] =>[orig_patent_app_number] => 11683495 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683495
Method and system for building binary decision diagrams optimally for nodes in a netlist graph using don't-caring Mar 7, 2007 Issued
Array ( [id] => 7598010 [patent_doc_number] => 07584443 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-01 [patent_title] => 'Clock domain conflict analysis for timing graphs' [patent_app_type] => utility [patent_app_number] => 11/683388 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6321 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/584/07584443.pdf [firstpage_image] =>[orig_patent_app_number] => 11683388 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/683388
Clock domain conflict analysis for timing graphs Mar 6, 2007 Issued
Array ( [id] => 5047672 [patent_doc_number] => 20070266346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method of Design For Manufacturing' [patent_app_type] => utility [patent_app_number] => 11/682378 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3908 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20070266346.pdf [firstpage_image] =>[orig_patent_app_number] => 11682378 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/682378
Method of design for manufacturing Mar 5, 2007 Issued
Array ( [id] => 166923 [patent_doc_number] => 07673257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-02 [patent_title] => 'System, method and computer program product for word-level operator-to-cell mapping' [patent_app_type] => utility [patent_app_number] => 11/682243 [patent_app_country] => US [patent_app_date] => 2007-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6339 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673257.pdf [firstpage_image] =>[orig_patent_app_number] => 11682243 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/682243
System, method and computer program product for word-level operator-to-cell mapping Mar 4, 2007 Issued
Array ( [id] => 241472 [patent_doc_number] => 07594198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Ultra fine pitch I/O design for microchips' [patent_app_type] => utility [patent_app_number] => 11/711949 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594198.pdf [firstpage_image] =>[orig_patent_app_number] => 11711949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711949
Ultra fine pitch I/O design for microchips Feb 26, 2007 Issued
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