Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5132632 [patent_doc_number] => 20070209029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'SLM Lithography: Printing to below K1=.30 without previous OPC processing' [patent_app_type] => utility [patent_app_number] => 11/710710 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 15822 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20070209029.pdf [firstpage_image] =>[orig_patent_app_number] => 11710710 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/710710
SLM lithography: printing to below K1=.30 without previous OPC processing Feb 25, 2007 Issued
Array ( [id] => 4730183 [patent_doc_number] => 20080209038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Methods and systems for optimizing placement on a clock signal distribution network' [patent_app_type] => utility [patent_app_number] => 11/710249 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7229 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20080209038.pdf [firstpage_image] =>[orig_patent_app_number] => 11710249 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/710249
Methods and systems for optimizing placement on a clock signal distribution network Feb 22, 2007 Abandoned
Array ( [id] => 4923882 [patent_doc_number] => 20080072199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Method for designing semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/709749 [patent_app_country] => US [patent_app_date] => 2007-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4255 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072199.pdf [firstpage_image] =>[orig_patent_app_number] => 11709749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/709749
Method for designing semiconductor integrated circuit Feb 22, 2007 Abandoned
Array ( [id] => 4979218 [patent_doc_number] => 20070220453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-20 [patent_title] => 'Method for forming reset operation verifying circuit' [patent_app_type] => utility [patent_app_number] => 11/703079 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5322 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20070220453.pdf [firstpage_image] =>[orig_patent_app_number] => 11703079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703079
Method for forming reset operation verifying circuit Feb 6, 2007 Abandoned
Array ( [id] => 4830518 [patent_doc_number] => 20080127010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Compact Chip Package Macromodels for Chip-Package Simulation' [patent_app_type] => utility [patent_app_number] => 11/563704 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6205 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127010.pdf [firstpage_image] =>[orig_patent_app_number] => 11563704 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563704
Compact chip package macromodels for chip-package simulation Nov 27, 2006 Issued
Array ( [id] => 329732 [patent_doc_number] => 07516426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Methods of improving operational parameters of pair of matched transistors and set of transistors' [patent_app_type] => utility [patent_app_number] => 11/561537 [patent_app_country] => US [patent_app_date] => 2006-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2304 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516426.pdf [firstpage_image] =>[orig_patent_app_number] => 11561537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/561537
Methods of improving operational parameters of pair of matched transistors and set of transistors Nov 19, 2006 Issued
Array ( [id] => 128305 [patent_doc_number] => 07707521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Layout architecture having high-performance and high-density design' [patent_app_type] => utility [patent_app_number] => 11/560838 [patent_app_country] => US [patent_app_date] => 2006-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2717 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/707/07707521.pdf [firstpage_image] =>[orig_patent_app_number] => 11560838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560838
Layout architecture having high-performance and high-density design Nov 16, 2006 Issued
Array ( [id] => 280198 [patent_doc_number] => 07559042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Layout evaluating apparatus' [patent_app_type] => utility [patent_app_number] => 11/560484 [patent_app_country] => US [patent_app_date] => 2006-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7037 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/559/07559042.pdf [firstpage_image] =>[orig_patent_app_number] => 11560484 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560484
Layout evaluating apparatus Nov 15, 2006 Issued
Array ( [id] => 5097215 [patent_doc_number] => 20070118824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR IMPROVING YIELD IN INTEGRATED CIRCUIT DEVICE FABRICATION AND RELATED DEVICES' [patent_app_type] => utility [patent_app_number] => 11/560006 [patent_app_country] => US [patent_app_date] => 2006-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8403 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20070118824.pdf [firstpage_image] =>[orig_patent_app_number] => 11560006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/560006
METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR IMPROVING YIELD IN INTEGRATED CIRCUIT DEVICE FABRICATION AND RELATED DEVICES Nov 14, 2006 Abandoned
Array ( [id] => 5226773 [patent_doc_number] => 20070256040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'CRITICAL AREA COMPUTATION OF COMPOSITE FAULT MECHANISMS USING VORONOI DIAGRAMS' [patent_app_type] => utility [patent_app_number] => 11/538913 [patent_app_country] => US [patent_app_date] => 2006-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20070256040.pdf [firstpage_image] =>[orig_patent_app_number] => 11538913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538913
Critical area computation of composite fault mechanisms using Voronoi diagrams Oct 4, 2006 Issued
Array ( [id] => 7692803 [patent_doc_number] => 20070016883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-18 [patent_title] => 'Clock Gating Circuit' [patent_app_type] => utility [patent_app_number] => 11/533497 [patent_app_country] => US [patent_app_date] => 2006-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2984 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20070016883.pdf [firstpage_image] =>[orig_patent_app_number] => 11533497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/533497
Clock gating circuit Sep 19, 2006 Issued
Array ( [id] => 4578100 [patent_doc_number] => 07823113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Automatic integrated circuit routing using spines' [patent_app_type] => utility [patent_app_number] => 11/530613 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 9478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823113.pdf [firstpage_image] =>[orig_patent_app_number] => 11530613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530613
Automatic integrated circuit routing using spines Sep 10, 2006 Issued
Array ( [id] => 6302837 [patent_doc_number] => 20100162185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'ELECTRONIC CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/063501 [patent_app_country] => US [patent_app_date] => 2006-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14439 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162185.pdf [firstpage_image] =>[orig_patent_app_number] => 12063501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/063501
ELECTRONIC CIRCUIT DESIGN Aug 10, 2006 Abandoned
Array ( [id] => 245207 [patent_doc_number] => 07590951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-15 [patent_title] => 'Plug-in component-based dependency management for partitions within an incremental implementation flow' [patent_app_type] => utility [patent_app_number] => 11/500525 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590951.pdf [firstpage_image] =>[orig_patent_app_number] => 11500525 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500525
Plug-in component-based dependency management for partitions within an incremental implementation flow Aug 7, 2006 Issued
Array ( [id] => 17596 [patent_doc_number] => 07805686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-28 [patent_title] => 'Methods to generate state space models by closed forms for general interconnect and transmission lines, trees and nets, and their model reduction and simulations' [patent_app_type] => utility [patent_app_number] => 11/500613 [patent_app_country] => US [patent_app_date] => 2006-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 11456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/805/07805686.pdf [firstpage_image] =>[orig_patent_app_number] => 11500613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500613
Methods to generate state space models by closed forms for general interconnect and transmission lines, trees and nets, and their model reduction and simulations Aug 7, 2006 Issued
Array ( [id] => 5006672 [patent_doc_number] => 20070204245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Method for accelerating the RC extraction in integrated circuit designs' [patent_app_type] => utility [patent_app_number] => 11/500727 [patent_app_country] => US [patent_app_date] => 2006-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2638 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20070204245.pdf [firstpage_image] =>[orig_patent_app_number] => 11500727 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/500727
Method for accelerating the RC extraction in integrated circuit designs Aug 6, 2006 Abandoned
Array ( [id] => 4690160 [patent_doc_number] => 20080034341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices' [patent_app_type] => utility [patent_app_number] => 11/499913 [patent_app_country] => US [patent_app_date] => 2006-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5659 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20080034341.pdf [firstpage_image] =>[orig_patent_app_number] => 11499913 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499913
Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices Aug 2, 2006 Issued
Array ( [id] => 137343 [patent_doc_number] => 07698662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-13 [patent_title] => 'System and method for proxied evaluation of PCells' [patent_app_type] => utility [patent_app_number] => 11/490678 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698662.pdf [firstpage_image] =>[orig_patent_app_number] => 11490678 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490678
System and method for proxied evaluation of PCells Jul 20, 2006 Issued
Array ( [id] => 206786 [patent_doc_number] => 07634743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-15 [patent_title] => 'Method for updating a placed and routed netlist' [patent_app_type] => utility [patent_app_number] => 11/490668 [patent_app_country] => US [patent_app_date] => 2006-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4032 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/634/07634743.pdf [firstpage_image] =>[orig_patent_app_number] => 11490668 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490668
Method for updating a placed and routed netlist Jul 20, 2006 Issued
Array ( [id] => 329776 [patent_doc_number] => 07516437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-07 [patent_title] => 'Skew-driven routing for networks' [patent_app_type] => utility [patent_app_number] => 11/490670 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3408 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516437.pdf [firstpage_image] =>[orig_patent_app_number] => 11490670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/490670
Skew-driven routing for networks Jul 19, 2006 Issued
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