Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5663222 [patent_doc_number] => 20060253818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Design checks for signal lines' [patent_app_type] => utility [patent_app_number] => 11/485598 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4180 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253818.pdf [firstpage_image] =>[orig_patent_app_number] => 11485598 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485598
Design checks for signal lines Jul 11, 2006 Abandoned
Array ( [id] => 810193 [patent_doc_number] => 07421673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Design checks for signal lines' [patent_app_type] => utility [patent_app_number] => 11/485603 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4212 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421673.pdf [firstpage_image] =>[orig_patent_app_number] => 11485603 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485603
Design checks for signal lines Jul 11, 2006 Issued
Array ( [id] => 5663221 [patent_doc_number] => 20060253817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Checks for signal lines' [patent_app_type] => utility [patent_app_number] => 11/485154 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4180 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253817.pdf [firstpage_image] =>[orig_patent_app_number] => 11485154 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/485154
Checks for signal lines Jul 11, 2006 Issued
Array ( [id] => 4996296 [patent_doc_number] => 20070011641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-11 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/482792 [patent_app_country] => US [patent_app_date] => 2006-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4624 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20070011641.pdf [firstpage_image] =>[orig_patent_app_number] => 11482792 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482792
Semiconductor integrated circuit device Jul 9, 2006 Abandoned
Array ( [id] => 97119 [patent_doc_number] => 07735027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Alignment of product representations' [patent_app_type] => utility [patent_app_number] => 11/482533 [patent_app_country] => US [patent_app_date] => 2006-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6160 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/735/07735027.pdf [firstpage_image] =>[orig_patent_app_number] => 11482533 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482533
Alignment of product representations Jul 6, 2006 Issued
Array ( [id] => 362960 [patent_doc_number] => 07487479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-03 [patent_title] => 'Systematic approach for applying recommended rules on a circuit layout' [patent_app_type] => utility [patent_app_number] => 11/482355 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6297 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487479.pdf [firstpage_image] =>[orig_patent_app_number] => 11482355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/482355
Systematic approach for applying recommended rules on a circuit layout Jul 5, 2006 Issued
Array ( [id] => 4447685 [patent_doc_number] => 07930659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Software verification' [patent_app_type] => utility [patent_app_number] => 11/422069 [patent_app_country] => US [patent_app_date] => 2006-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14483 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930659.pdf [firstpage_image] =>[orig_patent_app_number] => 11422069 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422069
Software verification Jun 2, 2006 Issued
Array ( [id] => 241469 [patent_doc_number] => 07594195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Multithreaded reachability' [patent_app_type] => utility [patent_app_number] => 11/421979 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3654 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594195.pdf [firstpage_image] =>[orig_patent_app_number] => 11421979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421979
Multithreaded reachability Jun 1, 2006 Issued
Array ( [id] => 5627173 [patent_doc_number] => 20060265678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Layout design program, layout design device and layout design method for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/435759 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12191 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265678.pdf [firstpage_image] =>[orig_patent_app_number] => 11435759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435759
Layout design program, layout design device and layout design method for semiconductor integrated circuit May 17, 2006 Issued
Array ( [id] => 4582469 [patent_doc_number] => 07840914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Distributing computations in a parallel processing environment' [patent_app_type] => utility [patent_app_number] => 11/433989 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9824 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840914.pdf [firstpage_image] =>[orig_patent_app_number] => 11433989 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433989
Distributing computations in a parallel processing environment May 14, 2006 Issued
Array ( [id] => 5184596 [patent_doc_number] => 20070055950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'SYSTEM AND METHOD FOR SELECTING MOSFETS SUITABLE FOR A CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 11/308458 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2428 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20070055950.pdf [firstpage_image] =>[orig_patent_app_number] => 11308458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308458
System and method for selecting MOSFETs suitable for a circuit design Mar 27, 2006 Issued
Array ( [id] => 5670283 [patent_doc_number] => 20060175637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh' [patent_app_type] => utility [patent_app_number] => 11/348802 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4572 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20060175637.pdf [firstpage_image] =>[orig_patent_app_number] => 11348802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348802
Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh Feb 6, 2006 Abandoned
Array ( [id] => 333365 [patent_doc_number] => 07512907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Generating rules for nets that cross package boundaries' [patent_app_type] => utility [patent_app_number] => 11/344928 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8150 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512907.pdf [firstpage_image] =>[orig_patent_app_number] => 11344928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/344928
Generating rules for nets that cross package boundaries Jan 31, 2006 Issued
Array ( [id] => 5179358 [patent_doc_number] => 20070180418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Clock scheme for circuit arrangement' [patent_app_type] => utility [patent_app_number] => 11/343018 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2446 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180418.pdf [firstpage_image] =>[orig_patent_app_number] => 11343018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/343018
Clock scheme for circuit arrangement Jan 29, 2006 Abandoned
Array ( [id] => 5137642 [patent_doc_number] => 20070079271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Design tool, design method, and program for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/339468 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2940 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079271.pdf [firstpage_image] =>[orig_patent_app_number] => 11339468 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/339468
Design tool, design method, and program for semiconductor device Jan 25, 2006 Abandoned
Array ( [id] => 5621354 [patent_doc_number] => 20060190889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Circuit floorplanning and placement by look-ahead enabled recursive partitioning' [patent_app_type] => utility [patent_app_number] => 11/331769 [patent_app_country] => US [patent_app_date] => 2006-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8939 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190889.pdf [firstpage_image] =>[orig_patent_app_number] => 11331769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/331769
Circuit floorplanning and placement by look-ahead enabled recursive partitioning Jan 15, 2006 Abandoned
Array ( [id] => 810194 [patent_doc_number] => 07421674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Apparatus and method for analyzing post-layout timing critical paths' [patent_app_type] => utility [patent_app_number] => 11/328708 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6835 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421674.pdf [firstpage_image] =>[orig_patent_app_number] => 11328708 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/328708
Apparatus and method for analyzing post-layout timing critical paths Jan 9, 2006 Issued
Array ( [id] => 294264 [patent_doc_number] => 07546564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Method for verifying optical proximity correction using layer versus layer comparison' [patent_app_type] => utility [patent_app_number] => 11/321579 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546564.pdf [firstpage_image] =>[orig_patent_app_number] => 11321579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321579
Method for verifying optical proximity correction using layer versus layer comparison Dec 27, 2005 Issued
Array ( [id] => 5692130 [patent_doc_number] => 20060152275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Signal transmitting circuit' [patent_app_type] => utility [patent_app_number] => 11/317359 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1085 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20060152275.pdf [firstpage_image] =>[orig_patent_app_number] => 11317359 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317359
Signal transmitting circuit Dec 22, 2005 Abandoned
Array ( [id] => 5633665 [patent_doc_number] => 20060150136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Systems and methods for designing integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/314569 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2900 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20060150136.pdf [firstpage_image] =>[orig_patent_app_number] => 11314569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314569
Systems and methods for designing integrated circuits Dec 20, 2005 Abandoned
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