Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 146974 [patent_doc_number] => 07694241 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-06 [patent_title] => 'Automated design process and method for multi-rail cells and connections' [patent_app_type] => utility [patent_app_number] => 11/313969 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3020 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694241.pdf [firstpage_image] =>[orig_patent_app_number] => 11313969 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313969
Automated design process and method for multi-rail cells and connections Dec 19, 2005 Issued
Array ( [id] => 5917054 [patent_doc_number] => 20060129964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Net list generating method and layout designing method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/297389 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4470 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129964.pdf [firstpage_image] =>[orig_patent_app_number] => 11297389 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297389
Net list generating method and layout designing method of semiconductor integrated circuit Dec 8, 2005 Abandoned
Array ( [id] => 5097216 [patent_doc_number] => 20070118825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Usage of a buildcode to specify layout characteristics' [patent_app_type] => utility [patent_app_number] => 11/284149 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3609 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20070118825.pdf [firstpage_image] =>[orig_patent_app_number] => 11284149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284149
Usage of a buildcode to specify layout characteristics Nov 20, 2005 Issued
Array ( [id] => 7687738 [patent_doc_number] => 20070106960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'System and method for the development and distribution of a VHDL intellectual property core' [patent_app_type] => utility [patent_app_number] => 11/270179 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106960.pdf [firstpage_image] =>[orig_patent_app_number] => 11270179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270179
System and method for the development and distribution of a VHDL intellectual property core Nov 8, 2005 Abandoned
11/269506 System with a defect tolerant configurable IC Nov 6, 2005 Abandoned
Array ( [id] => 5662608 [patent_doc_number] => 20060253204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Method and apparatus for designing and manufacturing electronic circuits subject to leakage problems caused by temperature variations and/or ageing' [patent_app_type] => utility [patent_app_number] => 11/252370 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15609 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253204.pdf [firstpage_image] =>[orig_patent_app_number] => 11252370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252370
Method and apparatus for designing and manufacturing electronic circuits subject to leakage problems caused by temperature variations and/or aging Oct 16, 2005 Issued
Array ( [id] => 5805197 [patent_doc_number] => 20060091550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same' [patent_app_type] => utility [patent_app_number] => 11/231810 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10230 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091550.pdf [firstpage_image] =>[orig_patent_app_number] => 11231810 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231810
Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same Sep 21, 2005 Abandoned
Array ( [id] => 451425 [patent_doc_number] => 07254791 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-07 [patent_title] => 'Method of measuring test coverage of backend verification runsets and automatically identifying ways to improve the test suite' [patent_app_type] => utility [patent_app_number] => 11/229085 [patent_app_country] => US [patent_app_date] => 2005-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5337 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254791.pdf [firstpage_image] =>[orig_patent_app_number] => 11229085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229085
Method of measuring test coverage of backend verification runsets and automatically identifying ways to improve the test suite Sep 15, 2005 Issued
Array ( [id] => 820208 [patent_doc_number] => 07412680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'Method and apparatus for performing integrated global routing and buffer insertion' [patent_app_type] => utility [patent_app_number] => 11/227680 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8136 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412680.pdf [firstpage_image] =>[orig_patent_app_number] => 11227680 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227680
Method and apparatus for performing integrated global routing and buffer insertion Sep 14, 2005 Issued
Array ( [id] => 600154 [patent_doc_number] => 07441208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => 'Methods for designing integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/225919 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3304 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441208.pdf [firstpage_image] =>[orig_patent_app_number] => 11225919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225919
Methods for designing integrated circuits Sep 12, 2005 Issued
Array ( [id] => 447592 [patent_doc_number] => 07257803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-14 [patent_title] => 'Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith' [patent_app_type] => utility [patent_app_number] => 11/224156 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7273 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/257/07257803.pdf [firstpage_image] =>[orig_patent_app_number] => 11224156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/224156
Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith Sep 11, 2005 Issued
Array ( [id] => 358640 [patent_doc_number] => 07490302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-10 [patent_title] => 'Power gating various number of resources based on utilization levels' [patent_app_type] => utility [patent_app_number] => 11/196179 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/490/07490302.pdf [firstpage_image] =>[orig_patent_app_number] => 11196179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196179
Power gating various number of resources based on utilization levels Aug 2, 2005 Issued
Array ( [id] => 591017 [patent_doc_number] => 07464345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Resource estimation for design planning' [patent_app_type] => utility [patent_app_number] => 11/194299 [patent_app_country] => US [patent_app_date] => 2005-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464345.pdf [firstpage_image] =>[orig_patent_app_number] => 11194299 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194299
Resource estimation for design planning Jul 31, 2005 Issued
Array ( [id] => 4632009 [patent_doc_number] => 08010919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Method for evaluating the quality of a computer program' [patent_app_type] => utility [patent_app_number] => 11/658931 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 6 [patent_no_of_words] => 2934 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010919.pdf [firstpage_image] =>[orig_patent_app_number] => 11658931 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/658931
Method for evaluating the quality of a computer program Jul 27, 2005 Issued
Array ( [id] => 5900664 [patent_doc_number] => 20060044932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'METHOD FOR ROUTING DATA PATHS IN A SEMICONDUCTOR CHIP WITH A PLURALITY OF LAYERS' [patent_app_type] => utility [patent_app_number] => 11/161159 [patent_app_country] => US [patent_app_date] => 2005-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3093 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044932.pdf [firstpage_image] =>[orig_patent_app_number] => 11161159 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/161159
Method for routing data paths in a semiconductor chip with a plurality of layers Jul 24, 2005 Issued
Array ( [id] => 605198 [patent_doc_number] => 07434194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Mask for fabricating semiconductor devices and method for designing the same' [patent_app_type] => utility [patent_app_number] => 11/187499 [patent_app_country] => US [patent_app_date] => 2005-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3212 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434194.pdf [firstpage_image] =>[orig_patent_app_number] => 11187499 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/187499
Mask for fabricating semiconductor devices and method for designing the same Jul 21, 2005 Issued
Array ( [id] => 823622 [patent_doc_number] => 07409658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-05 [patent_title] => 'Methods and systems for mixed-mode physical synthesis in electronic design automation' [patent_app_type] => utility [patent_app_number] => 11/140914 [patent_app_country] => US [patent_app_date] => 2005-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409658.pdf [firstpage_image] =>[orig_patent_app_number] => 11140914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/140914
Methods and systems for mixed-mode physical synthesis in electronic design automation May 31, 2005 Issued
Array ( [id] => 447581 [patent_doc_number] => 07257797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-14 [patent_title] => 'Method of automatic shape-based routing of interconnects in spines for integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/908895 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 9441 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/257/07257797.pdf [firstpage_image] =>[orig_patent_app_number] => 10908895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908895
Method of automatic shape-based routing of interconnects in spines for integrated circuit design May 30, 2005 Issued
Array ( [id] => 5610384 [patent_doc_number] => 20060271900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'SYSTEM AND METHOD TO IMPROVE CHIP YIELD, RELIABILITY AND PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 10/908803 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271900.pdf [firstpage_image] =>[orig_patent_app_number] => 10908803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908803
System and method to improve chip yield, reliability and performance May 25, 2005 Issued
Array ( [id] => 5610377 [patent_doc_number] => 20060271893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'METHOD FOR ISOLATING PROBLEM NETWORKS WITHIN AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 11/138835 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3099 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271893.pdf [firstpage_image] =>[orig_patent_app_number] => 11138835 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/138835
Method for isolating problem networks within an integrated circuit design May 25, 2005 Issued
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