Search

Suchin Parihar

Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1418
Issued Applications
1198
Pending Applications
84
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 241469 [patent_doc_number] => 07594195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Multithreaded reachability' [patent_app_type] => utility [patent_app_number] => 11/421979 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3654 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594195.pdf [firstpage_image] =>[orig_patent_app_number] => 11421979 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421979
Multithreaded reachability Jun 1, 2006 Issued
Array ( [id] => 5627173 [patent_doc_number] => 20060265678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Layout design program, layout design device and layout design method for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/435759 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12191 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265678.pdf [firstpage_image] =>[orig_patent_app_number] => 11435759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435759
Layout design program, layout design device and layout design method for semiconductor integrated circuit May 17, 2006 Issued
Array ( [id] => 4582469 [patent_doc_number] => 07840914 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Distributing computations in a parallel processing environment' [patent_app_type] => utility [patent_app_number] => 11/433989 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9824 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840914.pdf [firstpage_image] =>[orig_patent_app_number] => 11433989 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433989
Distributing computations in a parallel processing environment May 14, 2006 Issued
Array ( [id] => 5184596 [patent_doc_number] => 20070055950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'SYSTEM AND METHOD FOR SELECTING MOSFETS SUITABLE FOR A CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 11/308458 [patent_app_country] => US [patent_app_date] => 2006-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2428 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20070055950.pdf [firstpage_image] =>[orig_patent_app_number] => 11308458 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308458
System and method for selecting MOSFETs suitable for a circuit design Mar 27, 2006 Issued
Array ( [id] => 5670283 [patent_doc_number] => 20060175637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh' [patent_app_type] => utility [patent_app_number] => 11/348802 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4572 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20060175637.pdf [firstpage_image] =>[orig_patent_app_number] => 11348802 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348802
Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh Feb 6, 2006 Abandoned
Array ( [id] => 333365 [patent_doc_number] => 07512907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Generating rules for nets that cross package boundaries' [patent_app_type] => utility [patent_app_number] => 11/344928 [patent_app_country] => US [patent_app_date] => 2006-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8150 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512907.pdf [firstpage_image] =>[orig_patent_app_number] => 11344928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/344928
Generating rules for nets that cross package boundaries Jan 31, 2006 Issued
Array ( [id] => 5179358 [patent_doc_number] => 20070180418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'Clock scheme for circuit arrangement' [patent_app_type] => utility [patent_app_number] => 11/343018 [patent_app_country] => US [patent_app_date] => 2006-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2446 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20070180418.pdf [firstpage_image] =>[orig_patent_app_number] => 11343018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/343018
Clock scheme for circuit arrangement Jan 29, 2006 Abandoned
Array ( [id] => 5137642 [patent_doc_number] => 20070079271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Design tool, design method, and program for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/339468 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2940 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079271.pdf [firstpage_image] =>[orig_patent_app_number] => 11339468 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/339468
Design tool, design method, and program for semiconductor device Jan 25, 2006 Abandoned
Array ( [id] => 5621354 [patent_doc_number] => 20060190889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Circuit floorplanning and placement by look-ahead enabled recursive partitioning' [patent_app_type] => utility [patent_app_number] => 11/331769 [patent_app_country] => US [patent_app_date] => 2006-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8939 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190889.pdf [firstpage_image] =>[orig_patent_app_number] => 11331769 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/331769
Circuit floorplanning and placement by look-ahead enabled recursive partitioning Jan 15, 2006 Abandoned
Array ( [id] => 810194 [patent_doc_number] => 07421674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Apparatus and method for analyzing post-layout timing critical paths' [patent_app_type] => utility [patent_app_number] => 11/328708 [patent_app_country] => US [patent_app_date] => 2006-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6835 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421674.pdf [firstpage_image] =>[orig_patent_app_number] => 11328708 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/328708
Apparatus and method for analyzing post-layout timing critical paths Jan 9, 2006 Issued
Array ( [id] => 294264 [patent_doc_number] => 07546564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-09 [patent_title] => 'Method for verifying optical proximity correction using layer versus layer comparison' [patent_app_type] => utility [patent_app_number] => 11/321579 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546564.pdf [firstpage_image] =>[orig_patent_app_number] => 11321579 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/321579
Method for verifying optical proximity correction using layer versus layer comparison Dec 27, 2005 Issued
Array ( [id] => 5692130 [patent_doc_number] => 20060152275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Signal transmitting circuit' [patent_app_type] => utility [patent_app_number] => 11/317359 [patent_app_country] => US [patent_app_date] => 2005-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1085 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20060152275.pdf [firstpage_image] =>[orig_patent_app_number] => 11317359 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317359
Signal transmitting circuit Dec 22, 2005 Abandoned
Array ( [id] => 5633665 [patent_doc_number] => 20060150136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Systems and methods for designing integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/314569 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2900 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20060150136.pdf [firstpage_image] =>[orig_patent_app_number] => 11314569 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/314569
Systems and methods for designing integrated circuits Dec 20, 2005 Abandoned
Array ( [id] => 146974 [patent_doc_number] => 07694241 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-04-06 [patent_title] => 'Automated design process and method for multi-rail cells and connections' [patent_app_type] => utility [patent_app_number] => 11/313969 [patent_app_country] => US [patent_app_date] => 2005-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3020 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/694/07694241.pdf [firstpage_image] =>[orig_patent_app_number] => 11313969 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/313969
Automated design process and method for multi-rail cells and connections Dec 19, 2005 Issued
Array ( [id] => 5917054 [patent_doc_number] => 20060129964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Net list generating method and layout designing method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/297389 [patent_app_country] => US [patent_app_date] => 2005-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4470 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129964.pdf [firstpage_image] =>[orig_patent_app_number] => 11297389 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/297389
Net list generating method and layout designing method of semiconductor integrated circuit Dec 8, 2005 Abandoned
Array ( [id] => 5097216 [patent_doc_number] => 20070118825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Usage of a buildcode to specify layout characteristics' [patent_app_type] => utility [patent_app_number] => 11/284149 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3609 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20070118825.pdf [firstpage_image] =>[orig_patent_app_number] => 11284149 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284149
Usage of a buildcode to specify layout characteristics Nov 20, 2005 Issued
Array ( [id] => 7687738 [patent_doc_number] => 20070106960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'System and method for the development and distribution of a VHDL intellectual property core' [patent_app_type] => utility [patent_app_number] => 11/270179 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20070106960.pdf [firstpage_image] =>[orig_patent_app_number] => 11270179 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/270179
System and method for the development and distribution of a VHDL intellectual property core Nov 8, 2005 Abandoned
11/269506 System with a defect tolerant configurable IC Nov 6, 2005 Abandoned
Array ( [id] => 5662608 [patent_doc_number] => 20060253204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Method and apparatus for designing and manufacturing electronic circuits subject to leakage problems caused by temperature variations and/or ageing' [patent_app_type] => utility [patent_app_number] => 11/252370 [patent_app_country] => US [patent_app_date] => 2005-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15609 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253204.pdf [firstpage_image] =>[orig_patent_app_number] => 11252370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252370
Method and apparatus for designing and manufacturing electronic circuits subject to leakage problems caused by temperature variations and/or aging Oct 16, 2005 Issued
Array ( [id] => 5805197 [patent_doc_number] => 20060091550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same' [patent_app_type] => utility [patent_app_number] => 11/231810 [patent_app_country] => US [patent_app_date] => 2005-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10230 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091550.pdf [firstpage_image] =>[orig_patent_app_number] => 11231810 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/231810
Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same Sep 21, 2005 Abandoned
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