
Suchin Parihar
Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2872 |
| Total Applications | 1418 |
| Issued Applications | 1198 |
| Pending Applications | 84 |
| Abandoned Applications | 154 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 241469
[patent_doc_number] => 07594195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-09-22
[patent_title] => 'Multithreaded reachability'
[patent_app_type] => utility
[patent_app_number] => 11/421979
[patent_app_country] => US
[patent_app_date] => 2006-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3654
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/594/07594195.pdf
[firstpage_image] =>[orig_patent_app_number] => 11421979
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421979 | Multithreaded reachability | Jun 1, 2006 | Issued |
Array
(
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[patent_doc_number] => 20060265678
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-23
[patent_title] => 'Layout design program, layout design device and layout design method for semiconductor integrated circuit'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/435759 | Layout design program, layout design device and layout design method for semiconductor integrated circuit | May 17, 2006 | Issued |
Array
(
[id] => 4582469
[patent_doc_number] => 07840914
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[patent_issue_date] => 2010-11-23
[patent_title] => 'Distributing computations in a parallel processing environment'
[patent_app_type] => utility
[patent_app_number] => 11/433989
[patent_app_country] => US
[patent_app_date] => 2006-05-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/433989 | Distributing computations in a parallel processing environment | May 14, 2006 | Issued |
Array
(
[id] => 5184596
[patent_doc_number] => 20070055950
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-08
[patent_title] => 'SYSTEM AND METHOD FOR SELECTING MOSFETS SUITABLE FOR A CIRCUIT DESIGN'
[patent_app_type] => utility
[patent_app_number] => 11/308458
[patent_app_country] => US
[patent_app_date] => 2006-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[firstpage_image] =>[orig_patent_app_number] => 11308458
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/308458 | System and method for selecting MOSFETs suitable for a circuit design | Mar 27, 2006 | Issued |
Array
(
[id] => 5670283
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[patent_title] => 'Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh'
[patent_app_type] => utility
[patent_app_number] => 11/348802
[patent_app_country] => US
[patent_app_date] => 2006-02-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/348802 | Power line layouts of a macro cell and combined layouts of a macro cell and a power mesh | Feb 6, 2006 | Abandoned |
Array
(
[id] => 333365
[patent_doc_number] => 07512907
[patent_country] => US
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[patent_issue_date] => 2009-03-31
[patent_title] => 'Generating rules for nets that cross package boundaries'
[patent_app_type] => utility
[patent_app_number] => 11/344928
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/344928 | Generating rules for nets that cross package boundaries | Jan 31, 2006 | Issued |
Array
(
[id] => 5179358
[patent_doc_number] => 20070180418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-02
[patent_title] => 'Clock scheme for circuit arrangement'
[patent_app_type] => utility
[patent_app_number] => 11/343018
[patent_app_country] => US
[patent_app_date] => 2006-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[firstpage_image] =>[orig_patent_app_number] => 11343018
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/343018 | Clock scheme for circuit arrangement | Jan 29, 2006 | Abandoned |
Array
(
[id] => 5137642
[patent_doc_number] => 20070079271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-04-05
[patent_title] => 'Design tool, design method, and program for semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/339468
[patent_app_country] => US
[patent_app_date] => 2006-01-26
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[patent_drawing_sheets_cnt] => 8
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[firstpage_image] =>[orig_patent_app_number] => 11339468
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/339468 | Design tool, design method, and program for semiconductor device | Jan 25, 2006 | Abandoned |
Array
(
[id] => 5621354
[patent_doc_number] => 20060190889
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[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'Circuit floorplanning and placement by look-ahead enabled recursive partitioning'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/331769 | Circuit floorplanning and placement by look-ahead enabled recursive partitioning | Jan 15, 2006 | Abandoned |
Array
(
[id] => 810194
[patent_doc_number] => 07421674
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-02
[patent_title] => 'Apparatus and method for analyzing post-layout timing critical paths'
[patent_app_type] => utility
[patent_app_number] => 11/328708
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[patent_app_date] => 2006-01-10
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[patent_drawing_sheets_cnt] => 9
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/328708 | Apparatus and method for analyzing post-layout timing critical paths | Jan 9, 2006 | Issued |
Array
(
[id] => 294264
[patent_doc_number] => 07546564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-09
[patent_title] => 'Method for verifying optical proximity correction using layer versus layer comparison'
[patent_app_type] => utility
[patent_app_number] => 11/321579
[patent_app_country] => US
[patent_app_date] => 2005-12-28
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[pdf_file] => patents/07/546/07546564.pdf
[firstpage_image] =>[orig_patent_app_number] => 11321579
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/321579 | Method for verifying optical proximity correction using layer versus layer comparison | Dec 27, 2005 | Issued |
Array
(
[id] => 5692130
[patent_doc_number] => 20060152275
[patent_country] => US
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[patent_title] => 'Signal transmitting circuit'
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[firstpage_image] =>[orig_patent_app_number] => 11317359
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/317359 | Signal transmitting circuit | Dec 22, 2005 | Abandoned |
Array
(
[id] => 5633665
[patent_doc_number] => 20060150136
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[patent_kind] => A1
[patent_issue_date] => 2006-07-06
[patent_title] => 'Systems and methods for designing integrated circuits'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/314569 | Systems and methods for designing integrated circuits | Dec 20, 2005 | Abandoned |
Array
(
[id] => 146974
[patent_doc_number] => 07694241
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[patent_issue_date] => 2010-04-06
[patent_title] => 'Automated design process and method for multi-rail cells and connections'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/313969 | Automated design process and method for multi-rail cells and connections | Dec 19, 2005 | Issued |
Array
(
[id] => 5917054
[patent_doc_number] => 20060129964
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[patent_title] => 'Net list generating method and layout designing method of semiconductor integrated circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/297389 | Net list generating method and layout designing method of semiconductor integrated circuit | Dec 8, 2005 | Abandoned |
Array
(
[id] => 5097216
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/284149 | Usage of a buildcode to specify layout characteristics | Nov 20, 2005 | Issued |
Array
(
[id] => 7687738
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[patent_title] => 'System and method for the development and distribution of a VHDL intellectual property core'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/270179 | System and method for the development and distribution of a VHDL intellectual property core | Nov 8, 2005 | Abandoned |
| 11/269506 | System with a defect tolerant configurable IC | Nov 6, 2005 | Abandoned |
Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231810 | Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same | Sep 21, 2005 | Abandoned |