Search

Suchin Parihar

Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5627176 [patent_doc_number] => 20060265681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'AN AUTOMATED AND ELECTRICALLY ROBUST METHOD FOR PLACING POWER GATING SWITCHES IN VOLTAGE ISLANDS' [patent_app_type] => utility [patent_app_number] => 10/908619 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3453 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265681.pdf [firstpage_image] =>[orig_patent_app_number] => 10908619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908619
Automated and electrically robust method for placing power gating switches in voltage islands May 18, 2005 Issued
Array ( [id] => 427990 [patent_doc_number] => 07272802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'R-cells containing CDM clamps' [patent_app_type] => utility [patent_app_number] => 11/126880 [patent_app_country] => US [patent_app_date] => 2005-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5053 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272802.pdf [firstpage_image] =>[orig_patent_app_number] => 11126880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126880
R-cells containing CDM clamps May 10, 2005 Issued
Array ( [id] => 490770 [patent_doc_number] => 07222321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'System and method for manipulating an integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 11/125168 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 2129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222321.pdf [firstpage_image] =>[orig_patent_app_number] => 11125168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/125168
System and method for manipulating an integrated circuit layout May 9, 2005 Issued
Array ( [id] => 396982 [patent_doc_number] => 07299444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-20 [patent_title] => 'Interface for pin swap information' [patent_app_type] => utility [patent_app_number] => 11/095949 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6401 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299444.pdf [firstpage_image] =>[orig_patent_app_number] => 11095949 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095949
Interface for pin swap information Mar 30, 2005 Issued
Array ( [id] => 5755866 [patent_doc_number] => 20060225015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Various methods and apparatuses for flexible hierarchy grouping' [patent_app_type] => utility [patent_app_number] => 11/097027 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4983 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20060225015.pdf [firstpage_image] =>[orig_patent_app_number] => 11097027 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097027
Various methods and apparatuses for flexible hierarchy grouping Mar 30, 2005 Abandoned
Array ( [id] => 6962791 [patent_doc_number] => 20050216874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Computer-supported, automated method for the verification of analog circuits' [patent_app_type] => utility [patent_app_number] => 11/085595 [patent_app_country] => US [patent_app_date] => 2005-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3582 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216874.pdf [firstpage_image] =>[orig_patent_app_number] => 11085595 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/085595
Computer-supported, automated method for the verification of analog circuits Mar 21, 2005 Issued
Array ( [id] => 6968407 [patent_doc_number] => 20050235243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Method and system for deciding a wiring route' [patent_app_type] => utility [patent_app_number] => 11/083960 [patent_app_country] => US [patent_app_date] => 2005-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4347 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20050235243.pdf [firstpage_image] =>[orig_patent_app_number] => 11083960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/083960
Method and system for deciding a wiring route Mar 20, 2005 Issued
Array ( [id] => 4590127 [patent_doc_number] => 07861190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-28 [patent_title] => 'Power-driven timing analysis and placement for programmable logic' [patent_app_type] => utility [patent_app_number] => 10/907049 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6142 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861190.pdf [firstpage_image] =>[orig_patent_app_number] => 10907049 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907049
Power-driven timing analysis and placement for programmable logic Mar 16, 2005 Issued
Array ( [id] => 396973 [patent_doc_number] => 07299438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Method and apparatus for verifying semiconductor integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/080555 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 9607 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299438.pdf [firstpage_image] =>[orig_patent_app_number] => 11080555 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080555
Method and apparatus for verifying semiconductor integrated circuits Mar 15, 2005 Issued
Array ( [id] => 7108441 [patent_doc_number] => 20050205894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network' [patent_app_type] => utility [patent_app_number] => 11/080456 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4546 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20050205894.pdf [firstpage_image] =>[orig_patent_app_number] => 11080456 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/080456
Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network Mar 15, 2005 Abandoned
Array ( [id] => 313476 [patent_doc_number] => 07530044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Method for manufacturing a programmable system in package' [patent_app_type] => utility [patent_app_number] => 11/081820 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5482 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530044.pdf [firstpage_image] =>[orig_patent_app_number] => 11081820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/081820
Method for manufacturing a programmable system in package Mar 14, 2005 Issued
Array ( [id] => 379207 [patent_doc_number] => 07313780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'System and method for designing semiconductor photomasks' [patent_app_type] => utility [patent_app_number] => 11/078820 [patent_app_country] => US [patent_app_date] => 2005-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313780.pdf [firstpage_image] =>[orig_patent_app_number] => 11078820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078820
System and method for designing semiconductor photomasks Mar 9, 2005 Issued
Array ( [id] => 5682817 [patent_doc_number] => 20060199087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure field' [patent_app_type] => utility [patent_app_number] => 11/071809 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199087.pdf [firstpage_image] =>[orig_patent_app_number] => 11071809 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071809
Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure field Mar 2, 2005 Abandoned
Array ( [id] => 5684519 [patent_doc_number] => 20060200789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'Connectivity verification of IC (integrated circuit) mask layout database versus IC schematic; LVS check, (LVS: IC layout versus IC schematic) via the internet method and computer software' [patent_app_type] => utility [patent_app_number] => 11/071020 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2094 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200789.pdf [firstpage_image] =>[orig_patent_app_number] => 11071020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/071020
Connectivity verification of IC (integrated circuit) mask layout database versus IC schematic; LVS check, (LVS: IC layout versus IC schematic) via the internet method and computer software Mar 2, 2005 Abandoned
Array ( [id] => 7165067 [patent_doc_number] => 20050201134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'Memory component with asymmetrical contact row' [patent_app_type] => utility [patent_app_number] => 11/070281 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3690 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20050201134.pdf [firstpage_image] =>[orig_patent_app_number] => 11070281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/070281
Memory component with asymmetrical contact row Mar 2, 2005 Abandoned
Array ( [id] => 5620689 [patent_doc_number] => 20060190223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'SAMPLE PROBABILITY OF FAULT FUNCTION DETERMINATION USING CRITICAL DEFECT SIZE MAP' [patent_app_type] => utility [patent_app_number] => 10/906549 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7742 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190223.pdf [firstpage_image] =>[orig_patent_app_number] => 10906549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906549
Sample probability of fault function determination using critical defect size map Feb 23, 2005 Issued
Array ( [id] => 5621356 [patent_doc_number] => 20060190891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'METHOD FOR PLACING PROBING PAD AND COMPUTER READABLE RECORDING MEDIUM FOR STORING PROGRAM THEREOF' [patent_app_type] => utility [patent_app_number] => 10/906009 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2907 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190891.pdf [firstpage_image] =>[orig_patent_app_number] => 10906009 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906009
Method for placing probing pad and computer readable recording medium for storing program thereof Jan 30, 2005 Issued
Array ( [id] => 5905611 [patent_doc_number] => 20060047451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Apparatus and method for circuit diagram display, and computer product' [patent_app_type] => utility [patent_app_number] => 11/022969 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10780 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047451.pdf [firstpage_image] =>[orig_patent_app_number] => 11022969 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/022969
Apparatus and method for circuit diagram display, and computer product Dec 27, 2004 Abandoned
Array ( [id] => 453628 [patent_doc_number] => 07251801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Method of designing circuit board' [patent_app_type] => utility [patent_app_number] => 11/019156 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 34 [patent_no_of_words] => 7555 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/251/07251801.pdf [firstpage_image] =>[orig_patent_app_number] => 11019156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019156
Method of designing circuit board Dec 22, 2004 Issued
Array ( [id] => 5646453 [patent_doc_number] => 20060132185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Clock gating circuit' [patent_app_type] => utility [patent_app_number] => 11/018796 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2983 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20060132185.pdf [firstpage_image] =>[orig_patent_app_number] => 11018796 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018796
Clock gating circuit Dec 20, 2004 Issued
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