
Suchin Parihar
Examiner (ID: 4481, Phone: (571)272-6210 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2872 |
| Total Applications | 1385 |
| Issued Applications | 1167 |
| Pending Applications | 109 |
| Abandoned Applications | 148 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 832758
[patent_doc_number] => 07401307
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-15
[patent_title] => 'Slack sensitivity to parameter variation based timing analysis'
[patent_app_type] => utility
[patent_app_number] => 10/904309
[patent_app_country] => US
[patent_app_date] => 2004-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5182
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/401/07401307.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904309
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904309 | Slack sensitivity to parameter variation based timing analysis | Nov 2, 2004 | Issued |
Array
(
[id] => 5809525
[patent_doc_number] => 20060095881
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Power pad synthesizer for an integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 10/976719
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8470
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20060095881.pdf
[firstpage_image] =>[orig_patent_app_number] => 10976719
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/976719 | Power pad synthesizer for an integrated circuit design | Oct 28, 2004 | Issued |
Array
(
[id] => 379206
[patent_doc_number] => 07313779
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-12-25
[patent_title] => 'Method and system for tiling a bias design to facilitate efficient design rule checking'
[patent_app_type] => utility
[patent_app_number] => 10/964409
[patent_app_country] => US
[patent_app_date] => 2004-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2711
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/313/07313779.pdf
[firstpage_image] =>[orig_patent_app_number] => 10964409
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/964409 | Method and system for tiling a bias design to facilitate efficient design rule checking | Oct 11, 2004 | Issued |
Array
(
[id] => 473064
[patent_doc_number] => 07234120
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-19
[patent_title] => 'Fault isolation in a programmable logic device'
[patent_app_type] => utility
[patent_app_number] => 10/959389
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4045
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/234/07234120.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959389
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959389 | Fault isolation in a programmable logic device | Oct 5, 2004 | Issued |
Array
(
[id] => 7595665
[patent_doc_number] => 07620917
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-11-17
[patent_title] => 'Methods and apparatuses for automated circuit design'
[patent_app_type] => utility
[patent_app_number] => 10/958899
[patent_app_country] => US
[patent_app_date] => 2004-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8240
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/620/07620917.pdf
[firstpage_image] =>[orig_patent_app_number] => 10958899
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/958899 | Methods and apparatuses for automated circuit design | Oct 3, 2004 | Issued |
Array
(
[id] => 514092
[patent_doc_number] => 07207029
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Calculating etch proximity-correction using image-precision techniques'
[patent_app_type] => utility
[patent_app_number] => 10/955189
[patent_app_country] => US
[patent_app_date] => 2004-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3055
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/207/07207029.pdf
[firstpage_image] =>[orig_patent_app_number] => 10955189
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/955189 | Calculating etch proximity-correction using image-precision techniques | Sep 28, 2004 | Issued |
Array
(
[id] => 820199
[patent_doc_number] => 07412671
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-08-12
[patent_title] => 'Apparatus and method for verifying an integrated circuit pattern'
[patent_app_type] => utility
[patent_app_number] => 10/948540
[patent_app_country] => US
[patent_app_date] => 2004-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 22
[patent_no_of_words] => 4720
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/412/07412671.pdf
[firstpage_image] =>[orig_patent_app_number] => 10948540
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/948540 | Apparatus and method for verifying an integrated circuit pattern | Sep 23, 2004 | Issued |
Array
(
[id] => 810199
[patent_doc_number] => 07421676
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-09-02
[patent_title] => 'System and method for phase shift assignment'
[patent_app_type] => utility
[patent_app_number] => 10/942689
[patent_app_country] => US
[patent_app_date] => 2004-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 3999
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/421/07421676.pdf
[firstpage_image] =>[orig_patent_app_number] => 10942689
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/942689 | System and method for phase shift assignment | Sep 14, 2004 | Issued |
Array
(
[id] => 513948
[patent_doc_number] => 07207014
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Method for modular design of a computer system-on-a-chip'
[patent_app_type] => utility
[patent_app_number] => 10/938920
[patent_app_country] => US
[patent_app_date] => 2004-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 49
[patent_no_of_words] => 23887
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/207/07207014.pdf
[firstpage_image] =>[orig_patent_app_number] => 10938920
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938920 | Method for modular design of a computer system-on-a-chip | Sep 9, 2004 | Issued |
Array
(
[id] => 555945
[patent_doc_number] => 07181718
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-02-20
[patent_title] => 'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks'
[patent_app_type] => utility
[patent_app_number] => 10/928599
[patent_app_country] => US
[patent_app_date] => 2004-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5933
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/181/07181718.pdf
[firstpage_image] =>[orig_patent_app_number] => 10928599
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/928599 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks | Aug 26, 2004 | Issued |
Array
(
[id] => 423866
[patent_doc_number] => 07275227
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-09-25
[patent_title] => 'Method of checking optical proximity correction data'
[patent_app_type] => utility
[patent_app_number] => 10/711153
[patent_app_country] => US
[patent_app_date] => 2004-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 19
[patent_no_of_words] => 6256
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/275/07275227.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711153
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711153 | Method of checking optical proximity correction data | Aug 26, 2004 | Issued |
Array
(
[id] => 5903404
[patent_doc_number] => 20060046353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Optimizing dynamic power characteristics of an integrated circuit chip'
[patent_app_type] => utility
[patent_app_number] => 10/927919
[patent_app_country] => US
[patent_app_date] => 2004-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1853
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20060046353.pdf
[firstpage_image] =>[orig_patent_app_number] => 10927919
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/927919 | Optimizing dynamic power characteristics of an integrated circuit chip | Aug 25, 2004 | Issued |
Array
(
[id] => 5822230
[patent_doc_number] => 20060026543
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-02
[patent_title] => 'ACCURATE TIMING ANALYSIS OF INTEGRATED CIRCUITS WHEN COMBINATORIAL LOGIC OFFERS A LOAD'
[patent_app_type] => utility
[patent_app_number] => 10/710699
[patent_app_country] => US
[patent_app_date] => 2004-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3502
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0026/20060026543.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710699
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710699 | ACCURATE TIMING ANALYSIS OF INTEGRATED CIRCUITS WHEN COMBINATORIAL LOGIC OFFERS A LOAD | Jul 28, 2004 | Abandoned |
Array
(
[id] => 421635
[patent_doc_number] => 07278120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-02
[patent_title] => 'Methods and apparatuses for transient analyses of circuits'
[patent_app_type] => utility
[patent_app_number] => 10/897459
[patent_app_country] => US
[patent_app_date] => 2004-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11844
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/278/07278120.pdf
[firstpage_image] =>[orig_patent_app_number] => 10897459
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/897459 | Methods and apparatuses for transient analyses of circuits | Jul 22, 2004 | Issued |
Array
(
[id] => 537689
[patent_doc_number] => 07191419
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-13
[patent_title] => 'Method of timing model abstraction for circuits containing simultaneously switching internal signals'
[patent_app_type] => utility
[patent_app_number] => 10/897349
[patent_app_country] => US
[patent_app_date] => 2004-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4430
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/191/07191419.pdf
[firstpage_image] =>[orig_patent_app_number] => 10897349
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/897349 | Method of timing model abstraction for circuits containing simultaneously switching internal signals | Jul 21, 2004 | Issued |
Array
(
[id] => 7240109
[patent_doc_number] => 20050256921
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-17
[patent_title] => 'Delay calculation method, timing analysis method, calculation object network approximation method, and delay control method'
[patent_app_type] => utility
[patent_app_number] => 10/891496
[patent_app_country] => US
[patent_app_date] => 2004-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 10886
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20050256921.pdf
[firstpage_image] =>[orig_patent_app_number] => 10891496
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891496 | Delay calculation method, timing analysis method, calculation object network approximation method, and delay control method | Jul 14, 2004 | Abandoned |
Array
(
[id] => 5740017
[patent_doc_number] => 20060010408
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Placement of a clock signal supply network during design of integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/887599
[patent_app_country] => US
[patent_app_date] => 2004-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5655
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20060010408.pdf
[firstpage_image] =>[orig_patent_app_number] => 10887599
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/887599 | Placement of a clock signal supply network during design of integrated circuits | Jul 8, 2004 | Issued |
Array
(
[id] => 258238
[patent_doc_number] => 07577926
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Security-sensitive semiconductor product, particularly a smart-card chip'
[patent_app_type] => utility
[patent_app_number] => 10/564079
[patent_app_country] => US
[patent_app_date] => 2004-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2435
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/577/07577926.pdf
[firstpage_image] =>[orig_patent_app_number] => 10564079
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/564079 | Security-sensitive semiconductor product, particularly a smart-card chip | Jul 4, 2004 | Issued |
Array
(
[id] => 6979773
[patent_doc_number] => 20050289491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'Method and computer program for estimating cell delay from a table with added voltage swing'
[patent_app_type] => utility
[patent_app_number] => 10/879768
[patent_app_country] => US
[patent_app_date] => 2004-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3657
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0289/20050289491.pdf
[firstpage_image] =>[orig_patent_app_number] => 10879768
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/879768 | Device for estimating cell delay from a table with added voltage swing | Jun 27, 2004 | Issued |
Array
(
[id] => 6979776
[patent_doc_number] => 20050289494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-29
[patent_title] => 'I/O CIRCUIT POWER ROUTING SYSTEM AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 10/710182
[patent_app_country] => US
[patent_app_date] => 2004-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5605
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0289/20050289494.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710182
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710182 | I/O circuit power routing system and method | Jun 23, 2004 | Issued |