
Suchin Parihar
Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2825, 2851, 2872 |
| Total Applications | 1418 |
| Issued Applications | 1198 |
| Pending Applications | 84 |
| Abandoned Applications | 154 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4590127
[patent_doc_number] => 07861190
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-12-28
[patent_title] => 'Power-driven timing analysis and placement for programmable logic'
[patent_app_type] => utility
[patent_app_number] => 10/907049
[patent_app_country] => US
[patent_app_date] => 2005-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 6142
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/861/07861190.pdf
[firstpage_image] =>[orig_patent_app_number] => 10907049
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/907049 | Power-driven timing analysis and placement for programmable logic | Mar 16, 2005 | Issued |
Array
(
[id] => 7108441
[patent_doc_number] => 20050205894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network'
[patent_app_type] => utility
[patent_app_number] => 11/080456
[patent_app_country] => US
[patent_app_date] => 2005-03-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0205/20050205894.pdf
[firstpage_image] =>[orig_patent_app_number] => 11080456
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/080456 | Method for variability constraints in design of integrated circuits especially digital circuits which includes timing closure upon placement and routing of digital circuit or network | Mar 15, 2005 | Abandoned |
Array
(
[id] => 396973
[patent_doc_number] => 07299438
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-20
[patent_title] => 'Method and apparatus for verifying semiconductor integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/080555
[patent_app_country] => US
[patent_app_date] => 2005-03-16
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[pdf_file] => patents/07/299/07299438.pdf
[firstpage_image] =>[orig_patent_app_number] => 11080555
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/080555 | Method and apparatus for verifying semiconductor integrated circuits | Mar 15, 2005 | Issued |
Array
(
[id] => 313476
[patent_doc_number] => 07530044
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Method for manufacturing a programmable system in package'
[patent_app_type] => utility
[patent_app_number] => 11/081820
[patent_app_country] => US
[patent_app_date] => 2005-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/530/07530044.pdf
[firstpage_image] =>[orig_patent_app_number] => 11081820
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/081820 | Method for manufacturing a programmable system in package | Mar 14, 2005 | Issued |
Array
(
[id] => 379207
[patent_doc_number] => 07313780
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-12-25
[patent_title] => 'System and method for designing semiconductor photomasks'
[patent_app_type] => utility
[patent_app_number] => 11/078820
[patent_app_country] => US
[patent_app_date] => 2005-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4518
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/313/07313780.pdf
[firstpage_image] =>[orig_patent_app_number] => 11078820
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/078820 | System and method for designing semiconductor photomasks | Mar 9, 2005 | Issued |
Array
(
[id] => 7165067
[patent_doc_number] => 20050201134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-15
[patent_title] => 'Memory component with asymmetrical contact row'
[patent_app_type] => utility
[patent_app_number] => 11/070281
[patent_app_country] => US
[patent_app_date] => 2005-03-03
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0201/20050201134.pdf
[firstpage_image] =>[orig_patent_app_number] => 11070281
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/070281 | Memory component with asymmetrical contact row | Mar 2, 2005 | Abandoned |
Array
(
[id] => 5684519
[patent_doc_number] => 20060200789
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'Connectivity verification of IC (integrated circuit) mask layout database versus IC schematic; LVS check, (LVS: IC layout versus IC schematic) via the internet method and computer software'
[patent_app_type] => utility
[patent_app_number] => 11/071020
[patent_app_country] => US
[patent_app_date] => 2005-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2094
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[pdf_file] => publications/A1/0200/20060200789.pdf
[firstpage_image] =>[orig_patent_app_number] => 11071020
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/071020 | Connectivity verification of IC (integrated circuit) mask layout database versus IC schematic; LVS check, (LVS: IC layout versus IC schematic) via the internet method and computer software | Mar 2, 2005 | Abandoned |
Array
(
[id] => 5682817
[patent_doc_number] => 20060199087
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-09-07
[patent_title] => 'Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure field'
[patent_app_type] => utility
[patent_app_number] => 11/071809
[patent_app_country] => US
[patent_app_date] => 2005-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4919
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[pdf_file] => publications/A1/0199/20060199087.pdf
[firstpage_image] =>[orig_patent_app_number] => 11071809
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/071809 | Method of making an integrated circuit by modifying a design layout by accounting for a parameter that varies based on a location within an exposure field | Mar 2, 2005 | Abandoned |
Array
(
[id] => 5620689
[patent_doc_number] => 20060190223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'SAMPLE PROBABILITY OF FAULT FUNCTION DETERMINATION USING CRITICAL DEFECT SIZE MAP'
[patent_app_type] => utility
[patent_app_number] => 10/906549
[patent_app_country] => US
[patent_app_date] => 2005-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => publications/A1/0190/20060190223.pdf
[firstpage_image] =>[orig_patent_app_number] => 10906549
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906549 | Sample probability of fault function determination using critical defect size map | Feb 23, 2005 | Issued |
Array
(
[id] => 5621356
[patent_doc_number] => 20060190891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-24
[patent_title] => 'METHOD FOR PLACING PROBING PAD AND COMPUTER READABLE RECORDING MEDIUM FOR STORING PROGRAM THEREOF'
[patent_app_type] => utility
[patent_app_number] => 10/906009
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[firstpage_image] =>[orig_patent_app_number] => 10906009
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/906009 | Method for placing probing pad and computer readable recording medium for storing program thereof | Jan 30, 2005 | Issued |
Array
(
[id] => 5905611
[patent_doc_number] => 20060047451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Apparatus and method for circuit diagram display, and computer product'
[patent_app_type] => utility
[patent_app_number] => 11/022969
[patent_app_country] => US
[patent_app_date] => 2004-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[firstpage_image] =>[orig_patent_app_number] => 11022969
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/022969 | Apparatus and method for circuit diagram display, and computer product | Dec 27, 2004 | Abandoned |
Array
(
[id] => 453628
[patent_doc_number] => 07251801
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Method of designing circuit board'
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[firstpage_image] =>[orig_patent_app_number] => 11019156
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/019156 | Method of designing circuit board | Dec 22, 2004 | Issued |
Array
(
[id] => 5646453
[patent_doc_number] => 20060132185
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[patent_title] => 'Clock gating circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/018796 | Clock gating circuit | Dec 20, 2004 | Issued |
Array
(
[id] => 832758
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[patent_issue_date] => 2008-07-15
[patent_title] => 'Slack sensitivity to parameter variation based timing analysis'
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Array
(
[id] => 5809525
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Array
(
[id] => 379206
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[patent_title] => 'Method and system for tiling a bias design to facilitate efficient design rule checking'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/964409 | Method and system for tiling a bias design to facilitate efficient design rule checking | Oct 11, 2004 | Issued |
Array
(
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Array
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Array
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Array
(
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[patent_title] => 'Apparatus and method for verifying an integrated circuit pattern'
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[firstpage_image] =>[orig_patent_app_number] => 10948540
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/948540 | Apparatus and method for verifying an integrated circuit pattern | Sep 23, 2004 | Issued |