Search

Suchin Parihar

Examiner (ID: 4481)

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1385
Issued Applications
1167
Pending Applications
109
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7100749 [patent_doc_number] => 20050132321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method and apparatus for designing an integrated circuit using a mask-programmable fabric' [patent_app_type] => utility [patent_app_number] => 10/734399 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4668 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132321.pdf [firstpage_image] =>[orig_patent_app_number] => 10734399 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734399
Method and apparatus for designing an integrated circuit using a mask-programmable fabric Dec 11, 2003 Issued
Array ( [id] => 6992585 [patent_doc_number] => 20050091622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Method of grouping scan flops based on clock domains for scan testing' [patent_app_type] => utility [patent_app_number] => 10/695853 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2919 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091622.pdf [firstpage_image] =>[orig_patent_app_number] => 10695853 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695853
Method of grouping scan flops based on clock domains for scan testing Oct 27, 2003 Abandoned
Array ( [id] => 536154 [patent_doc_number] => 07194714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method of reducing instantaneous current draw and an integrated circuit made thereby' [patent_app_type] => utility [patent_app_number] => 10/605683 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3541 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194714.pdf [firstpage_image] =>[orig_patent_app_number] => 10605683 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605683
Method of reducing instantaneous current draw and an integrated circuit made thereby Oct 16, 2003 Issued
Array ( [id] => 6979800 [patent_doc_number] => 20050289518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Compiler and logic circuit design method' [patent_app_type] => utility [patent_app_number] => 10/531287 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 11855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289518.pdf [firstpage_image] =>[orig_patent_app_number] => 10531287 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/531287
Compiler and logic circuit design method Oct 6, 2003 Abandoned
Array ( [id] => 7282417 [patent_doc_number] => 20040064794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Symbolic model checking with dynamic model pruning' [patent_app_type] => new [patent_app_number] => 10/666619 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6617 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064794.pdf [firstpage_image] =>[orig_patent_app_number] => 10666619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666619
Symbolic model checking with dynamic model pruning Sep 16, 2003 Abandoned
Array ( [id] => 478731 [patent_doc_number] => 07231616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Method and apparatus for accelerating test case development' [patent_app_type] => utility [patent_app_number] => 10/645729 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3781 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231616.pdf [firstpage_image] =>[orig_patent_app_number] => 10645729 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/645729
Method and apparatus for accelerating test case development Aug 19, 2003 Issued
Array ( [id] => 5867227 [patent_doc_number] => 20060101359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method and device for verifying digital circuits' [patent_app_type] => utility [patent_app_number] => 10/525999 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4188 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101359.pdf [firstpage_image] =>[orig_patent_app_number] => 10525999 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/525999
Method and device for verifying digital circuits Aug 18, 2003 Issued
Array ( [id] => 7130252 [patent_doc_number] => 20040041281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor integrated circuit and method for designing semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/635505 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041281.pdf [firstpage_image] =>[orig_patent_app_number] => 10635505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635505
Semiconductor integrated circuit and method for designing semiconductor integrated circuit Aug 6, 2003 Abandoned
Array ( [id] => 6907253 [patent_doc_number] => 20050102648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Orientation dependent shielding for use with dipole illumination techniques' [patent_app_type] => utility [patent_app_number] => 10/626858 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7741 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102648.pdf [firstpage_image] =>[orig_patent_app_number] => 10626858 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626858
Orientation dependent shielding for use with dipole illumination techniques Jul 24, 2003 Issued
Array ( [id] => 895070 [patent_doc_number] => 07350176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-25 [patent_title] => 'Techniques for mapping to a shared lookup table mask' [patent_app_type] => utility [patent_app_number] => 10/622923 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5650 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/350/07350176.pdf [firstpage_image] =>[orig_patent_app_number] => 10622923 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622923
Techniques for mapping to a shared lookup table mask Jul 16, 2003 Issued
Array ( [id] => 555077 [patent_doc_number] => 07174530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'System and method of design for testability' [patent_app_type] => utility [patent_app_number] => 10/438541 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5199 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174530.pdf [firstpage_image] =>[orig_patent_app_number] => 10438541 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438541
System and method of design for testability May 13, 2003 Issued
Array ( [id] => 829385 [patent_doc_number] => 07404153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Method for the providing of a design, test and development environment and system for carrying out said method' [patent_app_type] => utility [patent_app_number] => 10/503909 [patent_app_country] => US [patent_app_date] => 2003-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4410 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404153.pdf [firstpage_image] =>[orig_patent_app_number] => 10503909 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/503909
Method for the providing of a design, test and development environment and system for carrying out said method Feb 6, 2003 Issued
Array ( [id] => 597250 [patent_doc_number] => 07454735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'ASIC clock floor planning method and structure' [patent_app_type] => utility [patent_app_number] => 10/539334 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2453 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454735.pdf [firstpage_image] =>[orig_patent_app_number] => 10539334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/539334
ASIC clock floor planning method and structure Dec 16, 2002 Issued
Array ( [id] => 7100732 [patent_doc_number] => 20050132313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Optimization of the design of a synchronous digital circuit' [patent_app_type] => utility [patent_app_number] => 10/493889 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132313.pdf [firstpage_image] =>[orig_patent_app_number] => 10493889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/493889
Optimization of the design of a synchronous digital circuit Sep 25, 2002 Issued
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