Suchin Parihar

Array ( [id] => 810199 [patent_doc_number] => 07421676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'System and method for phase shift assignment' [patent_app_type] => utility [patent_app_number] => 10/942689 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3999 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421676.pdf [firstpage_image] =>[orig_patent_app_number] => 10942689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 513948 [patent_doc_number] => 07207014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Method for modular design of a computer system-on-a-chip' [patent_app_type] => utility [patent_app_number] => 10/938920 [patent_app_country] => US [patent_app_date] => 2004-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 49 [patent_no_of_words] => 23887 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/207/07207014.pdf [firstpage_image] =>[orig_patent_app_number] => 10938920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 555945 [patent_doc_number] => 07181718 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-20 [patent_title] => 'Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks' [patent_app_type] => utility [patent_app_number] => 10/928599 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5933 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/181/07181718.pdf [firstpage_image] =>[orig_patent_app_number] => 10928599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 423866 [patent_doc_number] => 07275227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-25 [patent_title] => 'Method of checking optical proximity correction data' [patent_app_type] => utility [patent_app_number] => 10/711153 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6256 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275227.pdf [firstpage_image] =>[orig_patent_app_number] => 10711153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5903404 [patent_doc_number] => 20060046353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Optimizing dynamic power characteristics of an integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 10/927919 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1853 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046353.pdf [firstpage_image] =>[orig_patent_app_number] => 10927919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5822230 [patent_doc_number] => 20060026543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'ACCURATE TIMING ANALYSIS OF INTEGRATED CIRCUITS WHEN COMBINATORIAL LOGIC OFFERS A LOAD' [patent_app_type] => utility [patent_app_number] => 10/710699 [patent_app_country] => US [patent_app_date] => 2004-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3502 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026543.pdf [firstpage_image] =>[orig_patent_app_number] => 10710699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 421635 [patent_doc_number] => 07278120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Methods and apparatuses for transient analyses of circuits' [patent_app_type] => utility [patent_app_number] => 10/897459 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11844 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/278/07278120.pdf [firstpage_image] =>[orig_patent_app_number] => 10897459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 537689 [patent_doc_number] => 07191419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Method of timing model abstraction for circuits containing simultaneously switching internal signals' [patent_app_type] => utility [patent_app_number] => 10/897349 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4430 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191419.pdf [firstpage_image] =>[orig_patent_app_number] => 10897349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7240109 [patent_doc_number] => 20050256921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Delay calculation method, timing analysis method, calculation object network approximation method, and delay control method' [patent_app_type] => utility [patent_app_number] => 10/891496 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10886 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20050256921.pdf [firstpage_image] =>[orig_patent_app_number] => 10891496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5740017 [patent_doc_number] => 20060010408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Placement of a clock signal supply network during design of integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/887599 [patent_app_country] => US [patent_app_date] => 2004-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010408.pdf [firstpage_image] =>[orig_patent_app_number] => 10887599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 258238 [patent_doc_number] => 07577926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-18 [patent_title] => 'Security-sensitive semiconductor product, particularly a smart-card chip' [patent_app_type] => utility [patent_app_number] => 10/564079 [patent_app_country] => US [patent_app_date] => 2004-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2435 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/577/07577926.pdf [firstpage_image] =>[orig_patent_app_number] => 10564079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6979773 [patent_doc_number] => 20050289491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Method and computer program for estimating cell delay from a table with added voltage swing' [patent_app_type] => utility [patent_app_number] => 10/879768 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3657 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289491.pdf [firstpage_image] =>[orig_patent_app_number] => 10879768 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6979776 [patent_doc_number] => 20050289494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'I/O CIRCUIT POWER ROUTING SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 10/710182 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289494.pdf [firstpage_image] =>[orig_patent_app_number] => 10710182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7605588 [patent_doc_number] => 07100135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Method and system to evaluate signal line spacing' [patent_app_type] => utility [patent_app_number] => 10/871809 [patent_app_country] => US [patent_app_date] => 2004-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4180 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100135.pdf [firstpage_image] =>[orig_patent_app_number] => 10871809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7256131 [patent_doc_number] => 20050273735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Tuple propagator and its use in analysis of mixed clock domain designs' [patent_app_type] => utility [patent_app_number] => 10/869488 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8867 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20050273735.pdf [firstpage_image] =>[orig_patent_app_number] => 10869488 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 609709 [patent_doc_number] => 07155691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Apparatus and methods for compiled static timing analysis' [patent_app_type] => utility [patent_app_number] => 10/862018 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12447 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155691.pdf [firstpage_image] =>[orig_patent_app_number] => 10862018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 418384 [patent_doc_number] => 07281222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-10-09 [patent_title] => 'System and method for automatic generation of optical proximity correction (OPC) rule sets' [patent_app_type] => utility [patent_app_number] => 10/859278 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4876 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/281/07281222.pdf [firstpage_image] =>[orig_patent_app_number] => 10859278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7057487 [patent_doc_number] => 20050278662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'METHOD FOR PREVENTING CIRCUIT FAILURES DUE TO GATE OXIDE LEAKAGE' [patent_app_type] => utility [patent_app_number] => 10/709798 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278662.pdf [firstpage_image] =>[orig_patent_app_number] => 10709798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7057092 [patent_doc_number] => 20050278267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Method and apparatus for supporting development of integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/857278 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4276 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278267.pdf [firstpage_image] =>[orig_patent_app_number] => 10857278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 407413 [patent_doc_number] => 07290238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Method, system and program product for building an automated datapath system generating tool' [patent_app_type] => utility [patent_app_number] => 10/709528 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11848 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/290/07290238.pdf [firstpage_image] =>[orig_patent_app_number] => 10709528 [rel_patent_id] =>[rel_patent_doc_number] =>)