Suchin Parihar

Array ( [id] => 536172 [patent_doc_number] => 07194716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Apparatus and methods for cell models for timing and power analysis' [patent_app_type] => utility [patent_app_number] => 10/839787 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7099 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194716.pdf [firstpage_image] =>[orig_patent_app_number] => 10839787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 623490 [patent_doc_number] => 07143371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Critical area computation of composite fault mechanisms using voronoi diagrams' [patent_app_type] => utility [patent_app_number] => 10/709293 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4207 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143371.pdf [firstpage_image] =>[orig_patent_app_number] => 10709293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 494354 [patent_doc_number] => 07219317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Method and computer program for verifying an incremental change to an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/828408 [patent_app_country] => US [patent_app_date] => 2004-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/219/07219317.pdf [firstpage_image] =>[orig_patent_app_number] => 10828408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6968395 [patent_doc_number] => 20050235231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'System and method for charge-balanced, continuous-write mask and wafer process for improved colinearity' [patent_app_type] => utility [patent_app_number] => 10/823981 [patent_app_country] => US [patent_app_date] => 2004-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3804 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20050235231.pdf [firstpage_image] =>[orig_patent_app_number] => 10823981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6954047 [patent_doc_number] => 20050229142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'System and method for automated accurate pre-layout estimation of standard cell characteristics' [patent_app_type] => utility [patent_app_number] => 10/822158 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4316 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229142.pdf [firstpage_image] =>[orig_patent_app_number] => 10822158 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6954044 [patent_doc_number] => 20050229139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Block-based processing in a packet-based reconfigurable architecture' [patent_app_type] => utility [patent_app_number] => 10/813461 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7188 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229139.pdf [firstpage_image] =>[orig_patent_app_number] => 10813461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 649163 [patent_doc_number] => 07120881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Wiring graphic verification method, program and apparatus' [patent_app_type] => utility [patent_app_number] => 10/805478 [patent_app_country] => US [patent_app_date] => 2004-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 43 [patent_no_of_words] => 11096 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120881.pdf [firstpage_image] =>[orig_patent_app_number] => 10805478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 427988 [patent_doc_number] => 07272801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-18 [patent_title] => 'System and method for process-flexible MEMS design and simulation' [patent_app_type] => utility [patent_app_number] => 10/799391 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5126 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/272/07272801.pdf [firstpage_image] =>[orig_patent_app_number] => 10799391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7354302 [patent_doc_number] => 20040194045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Electronic circuit design apparatus and method thereof' [patent_app_type] => new [patent_app_number] => 10/798261 [patent_app_country] => US [patent_app_date] => 2004-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5592 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20040194045.pdf [firstpage_image] =>[orig_patent_app_number] => 10798261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6943580 [patent_doc_number] => 20050195629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Interchangeable connection arrays for double-sided memory module placement' [patent_app_type] => utility [patent_app_number] => 10/792350 [patent_app_country] => US [patent_app_date] => 2004-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2609 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20050195629.pdf [firstpage_image] =>[orig_patent_app_number] => 10792350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 379185 [patent_doc_number] => 07313769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-25 [patent_title] => 'Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin' [patent_app_type] => utility [patent_app_number] => 10/790381 [patent_app_country] => US [patent_app_date] => 2004-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313769.pdf [firstpage_image] =>[orig_patent_app_number] => 10790381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7006934 [patent_doc_number] => 20050172247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'IC design modeling allowing dimension-dependent rule checking' [patent_app_type] => utility [patent_app_number] => 10/708039 [patent_app_country] => US [patent_app_date] => 2004-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10463 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20050172247.pdf [firstpage_image] =>[orig_patent_app_number] => 10708039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5778601 [patent_doc_number] => 20060107241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Evaluation device and circuit design method used for the same' [patent_app_type] => utility [patent_app_number] => 10/540973 [patent_app_country] => US [patent_app_date] => 2003-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7740 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20060107241.pdf [firstpage_image] =>[orig_patent_app_number] => 10540973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7100749 [patent_doc_number] => 20050132321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method and apparatus for designing an integrated circuit using a mask-programmable fabric' [patent_app_type] => utility [patent_app_number] => 10/734399 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4668 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132321.pdf [firstpage_image] =>[orig_patent_app_number] => 10734399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6992585 [patent_doc_number] => 20050091622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Method of grouping scan flops based on clock domains for scan testing' [patent_app_type] => utility [patent_app_number] => 10/695853 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2919 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091622.pdf [firstpage_image] =>[orig_patent_app_number] => 10695853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 536154 [patent_doc_number] => 07194714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method of reducing instantaneous current draw and an integrated circuit made thereby' [patent_app_type] => utility [patent_app_number] => 10/605683 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3541 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194714.pdf [firstpage_image] =>[orig_patent_app_number] => 10605683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6979800 [patent_doc_number] => 20050289518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Compiler and logic circuit design method' [patent_app_type] => utility [patent_app_number] => 10/531287 [patent_app_country] => US [patent_app_date] => 2003-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 11855 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20050289518.pdf [firstpage_image] =>[orig_patent_app_number] => 10531287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7282417 [patent_doc_number] => 20040064794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Symbolic model checking with dynamic model pruning' [patent_app_type] => new [patent_app_number] => 10/666619 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6617 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064794.pdf [firstpage_image] =>[orig_patent_app_number] => 10666619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 478731 [patent_doc_number] => 07231616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Method and apparatus for accelerating test case development' [patent_app_type] => utility [patent_app_number] => 10/645729 [patent_app_country] => US [patent_app_date] => 2003-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3781 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231616.pdf [firstpage_image] =>[orig_patent_app_number] => 10645729 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5867227 [patent_doc_number] => 20060101359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method and device for verifying digital circuits' [patent_app_type] => utility [patent_app_number] => 10/525999 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4188 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101359.pdf [firstpage_image] =>[orig_patent_app_number] => 10525999 [rel_patent_id] =>[rel_patent_doc_number] =>)