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Suchin Parihar

Examiner (ID: 4041, Phone: (571)272-6210 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851, 2872
Total Applications
1418
Issued Applications
1198
Pending Applications
84
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7130252 [patent_doc_number] => 20040041281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor integrated circuit and method for designing semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/635505 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041281.pdf [firstpage_image] =>[orig_patent_app_number] => 10635505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635505
Semiconductor integrated circuit and method for designing semiconductor integrated circuit Aug 6, 2003 Abandoned
Array ( [id] => 6907253 [patent_doc_number] => 20050102648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Orientation dependent shielding for use with dipole illumination techniques' [patent_app_type] => utility [patent_app_number] => 10/626858 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7741 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102648.pdf [firstpage_image] =>[orig_patent_app_number] => 10626858 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626858
Orientation dependent shielding for use with dipole illumination techniques Jul 24, 2003 Issued
Array ( [id] => 895070 [patent_doc_number] => 07350176 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-25 [patent_title] => 'Techniques for mapping to a shared lookup table mask' [patent_app_type] => utility [patent_app_number] => 10/622923 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5650 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/350/07350176.pdf [firstpage_image] =>[orig_patent_app_number] => 10622923 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622923
Techniques for mapping to a shared lookup table mask Jul 16, 2003 Issued
Array ( [id] => 555077 [patent_doc_number] => 07174530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'System and method of design for testability' [patent_app_type] => utility [patent_app_number] => 10/438541 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5199 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174530.pdf [firstpage_image] =>[orig_patent_app_number] => 10438541 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438541
System and method of design for testability May 13, 2003 Issued
Array ( [id] => 829385 [patent_doc_number] => 07404153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Method for the providing of a design, test and development environment and system for carrying out said method' [patent_app_type] => utility [patent_app_number] => 10/503909 [patent_app_country] => US [patent_app_date] => 2003-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4410 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404153.pdf [firstpage_image] =>[orig_patent_app_number] => 10503909 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/503909
Method for the providing of a design, test and development environment and system for carrying out said method Feb 6, 2003 Issued
Array ( [id] => 597250 [patent_doc_number] => 07454735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'ASIC clock floor planning method and structure' [patent_app_type] => utility [patent_app_number] => 10/539334 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2453 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454735.pdf [firstpage_image] =>[orig_patent_app_number] => 10539334 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/539334
ASIC clock floor planning method and structure Dec 16, 2002 Issued
Array ( [id] => 7100732 [patent_doc_number] => 20050132313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Optimization of the design of a synchronous digital circuit' [patent_app_type] => utility [patent_app_number] => 10/493889 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5687 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20050132313.pdf [firstpage_image] =>[orig_patent_app_number] => 10493889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/493889
Optimization of the design of a synchronous digital circuit Sep 25, 2002 Issued
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