Sue Hagarman

Array ( [id] => 300189 [patent_doc_number] => 07538393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Field insulator FET device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/935070 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2969 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538393.pdf [firstpage_image] =>[orig_patent_app_number] => 11935070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6231264 [patent_doc_number] => 20100264478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'METHOD TO REDUCE TRENCH CAPACITOR LEAKAGE FOR RANDOM ACCESS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/680017 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2928 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20100264478.pdf [firstpage_image] =>[orig_patent_app_number] => 12680017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 229209 [patent_doc_number] => 07602024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology' [patent_app_type] => utility [patent_app_number] => 11/980228 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 217 [patent_figures_cnt] => 275 [patent_no_of_words] => 34854 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 703 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602024.pdf [firstpage_image] =>[orig_patent_app_number] => 11980228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4701855 [patent_doc_number] => 20080061377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology' [patent_app_type] => utility [patent_app_number] => 11/980265 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 218 [patent_no_of_words] => 34816 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061377.pdf [firstpage_image] =>[orig_patent_app_number] => 11980265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4820716 [patent_doc_number] => 20080122006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology' [patent_app_type] => utility [patent_app_number] => 11/978901 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 218 [patent_no_of_words] => 34830 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122006.pdf [firstpage_image] =>[orig_patent_app_number] => 11978901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4732399 [patent_doc_number] => 20080049378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATING SAME' [patent_app_type] => utility [patent_app_number] => 11/927774 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3856 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049378.pdf [firstpage_image] =>[orig_patent_app_number] => 11927774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4701854 [patent_doc_number] => 20080061376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit & power transistor technology' [patent_app_type] => utility [patent_app_number] => 11/980051 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 218 [patent_no_of_words] => 34818 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061376.pdf [firstpage_image] =>[orig_patent_app_number] => 11980051 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4701853 [patent_doc_number] => 20080061375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology' [patent_app_type] => utility [patent_app_number] => 11/978854 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 218 [patent_figures_cnt] => 218 [patent_no_of_words] => 34817 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20080061375.pdf [firstpage_image] =>[orig_patent_app_number] => 11978854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9678908 [patent_doc_number] => 08817830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-26 [patent_title] => 'Saturable absorbers for Q-switching of middle infrared laser cavaties' [patent_app_type] => utility [patent_app_number] => 11/925148 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2493 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11925148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4557807 [patent_doc_number] => 07838371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Method of manufacturing a FET gate' [patent_app_type] => utility [patent_app_number] => 12/513548 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1864 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838371.pdf [firstpage_image] =>[orig_patent_app_number] => 12513548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 800325 [patent_doc_number] => 07425467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-16 [patent_title] => 'Web process interconnect in electronic assemblies' [patent_app_type] => utility [patent_app_number] => 11/869665 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 41 [patent_no_of_words] => 7472 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/425/07425467.pdf [firstpage_image] =>[orig_patent_app_number] => 11869665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4839665 [patent_doc_number] => 20080280151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'COPPER DIFFUSION BARRIER' [patent_app_type] => utility [patent_app_number] => 11/867708 [patent_app_country] => US [patent_app_date] => 2007-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2952 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20080280151.pdf [firstpage_image] =>[orig_patent_app_number] => 11867708 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4906335 [patent_doc_number] => 20080017101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Germanium Deposition' [patent_app_type] => utility [patent_app_number] => 11/867318 [patent_app_country] => US [patent_app_date] => 2007-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20080017101.pdf [firstpage_image] =>[orig_patent_app_number] => 11867318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 162343 [patent_doc_number] => 07670933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-02 [patent_title] => 'Nanowire-templated lateral epitaxial growth of non-polar group III nitrides' [patent_app_type] => utility [patent_app_number] => 11/866748 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2670 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/670/07670933.pdf [firstpage_image] =>[orig_patent_app_number] => 11866748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 81550 [patent_doc_number] => 07745315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-29 [patent_title] => 'Highly aligned vertical GaN nanowires using submonolayer metal catalysts' [patent_app_type] => utility [patent_app_number] => 11/866684 [patent_app_country] => US [patent_app_date] => 2007-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3843 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/745/07745315.pdf [firstpage_image] =>[orig_patent_app_number] => 11866684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4942789 [patent_doc_number] => 20080080112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'INTEGRATED CIRCUIT CHIPS WITH FINE-LINE METAL AND OVER-PASSIVATION METAL' [patent_app_type] => utility [patent_app_number] => 11/864927 [patent_app_country] => US [patent_app_date] => 2007-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 72 [patent_no_of_words] => 79789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080112.pdf [firstpage_image] =>[orig_patent_app_number] => 11864927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 71660 [patent_doc_number] => 07754621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Process for producing zirconium oxide thin films' [patent_app_type] => utility [patent_app_number] => 11/864663 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6590 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/754/07754621.pdf [firstpage_image] =>[orig_patent_app_number] => 11864663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5427691 [patent_doc_number] => 20090087001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'Decorative loudspeaker grille' [patent_app_type] => utility [patent_app_number] => 11/862198 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 860 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20090087001.pdf [firstpage_image] =>[orig_patent_app_number] => 11862198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 267058 [patent_doc_number] => 07566583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Method of determining adhesion quality' [patent_app_type] => utility [patent_app_number] => 11/855086 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3972 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566583.pdf [firstpage_image] =>[orig_patent_app_number] => 11855086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5452806 [patent_doc_number] => 20090068843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'METHOD OF FORMING MARK IN IC-FABRICATING PROCESS' [patent_app_type] => utility [patent_app_number] => 11/851938 [patent_app_country] => US [patent_app_date] => 2007-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10664 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20090068843.pdf [firstpage_image] =>[orig_patent_app_number] => 11851938 [rel_patent_id] =>[rel_patent_doc_number] =>)