Sue Hagarman

Array ( [id] => 6939243 [patent_doc_number] => 20050112806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby' [patent_app_type] => utility [patent_app_number] => 11/024777 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7677 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112806.pdf [firstpage_image] =>[orig_patent_app_number] => 11024777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 907147 [patent_doc_number] => 07332421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-19 [patent_title] => 'Method of fabricating gate electrode of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/024437 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1901 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/332/07332421.pdf [firstpage_image] =>[orig_patent_app_number] => 11024437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7253683 [patent_doc_number] => 20050142823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method of fabricating gate electrode of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/026287 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1974 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142823.pdf [firstpage_image] =>[orig_patent_app_number] => 11026287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 432228 [patent_doc_number] => 07265001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Methods of fabricating semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/025377 [patent_app_country] => US [patent_app_date] => 2004-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265001.pdf [firstpage_image] =>[orig_patent_app_number] => 11025377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6944876 [patent_doc_number] => 20050196925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Method of forming stress-relaxed SiGe buffer layer' [patent_app_type] => utility [patent_app_number] => 11/018647 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3620 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20050196925.pdf [firstpage_image] =>[orig_patent_app_number] => 11018647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6905717 [patent_doc_number] => 20050101112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Methods of nanotubes films and articles' [patent_app_type] => utility [patent_app_number] => 11/010491 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9272 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20050101112.pdf [firstpage_image] =>[orig_patent_app_number] => 11010491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 902861 [patent_doc_number] => 07335528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Methods of nanotube films and articles' [patent_app_type] => utility [patent_app_number] => 11/007752 [patent_app_country] => US [patent_app_date] => 2004-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 9290 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/335/07335528.pdf [firstpage_image] =>[orig_patent_app_number] => 11007752 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 548538 [patent_doc_number] => 07164209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-16 [patent_title] => 'Methods of positioning and/or orienting nanostructures' [patent_app_type] => utility [patent_app_number] => 11/000557 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9514 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164209.pdf [firstpage_image] =>[orig_patent_app_number] => 11000557 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 475242 [patent_doc_number] => 07226875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-05 [patent_title] => 'Method for enhancing FSG film stability' [patent_app_type] => utility [patent_app_number] => 10/999547 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4495 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/226/07226875.pdf [firstpage_image] =>[orig_patent_app_number] => 10999547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 23707 [patent_doc_number] => 07795150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Metal capping of damascene structures to improve reliability using hyper selective chemical-mechanical deposition' [patent_app_type] => utility [patent_app_number] => 10/998467 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3344 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/795/07795150.pdf [firstpage_image] =>[orig_patent_app_number] => 10998467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 380067 [patent_doc_number] => 07309641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'Method for rounding bottom corners of trench and shallow trench isolation process' [patent_app_type] => utility [patent_app_number] => 10/997507 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1615 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/309/07309641.pdf [firstpage_image] =>[orig_patent_app_number] => 10997507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5862393 [patent_doc_number] => 20060096523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Method for producing crystals and screening crystallization conditions' [patent_app_type] => utility [patent_app_number] => 10/985307 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7861 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20060096523.pdf [firstpage_image] =>[orig_patent_app_number] => 10985307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 531034 [patent_doc_number] => 07179738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Semiconductor assembly having substrate with electroplated contact pads' [patent_app_type] => utility [patent_app_number] => 10/985757 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3547 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/179/07179738.pdf [firstpage_image] =>[orig_patent_app_number] => 10985757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6915461 [patent_doc_number] => 20050093022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Spacer chalcogenide memory device' [patent_app_type] => utility [patent_app_number] => 10/983437 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1994 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093022.pdf [firstpage_image] =>[orig_patent_app_number] => 10983437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7097982 [patent_doc_number] => 20050130441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Semiconductor devices and methods of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/981987 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1519 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130441.pdf [firstpage_image] =>[orig_patent_app_number] => 10981987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 428587 [patent_doc_number] => 07268021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Lead frame and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/981417 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6051 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268021.pdf [firstpage_image] =>[orig_patent_app_number] => 10981417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 869645 [patent_doc_number] => 07365410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Semiconductor structure having a metallic buffer layer and method for forming' [patent_app_type] => utility [patent_app_number] => 10/977727 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1619 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/365/07365410.pdf [firstpage_image] =>[orig_patent_app_number] => 10977727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5807867 [patent_doc_number] => 20060094222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Integrated circuit die configuration for packaging' [patent_app_type] => utility [patent_app_number] => 10/977157 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4160 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20060094222.pdf [firstpage_image] =>[orig_patent_app_number] => 10977157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 708698 [patent_doc_number] => 07061075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-13 [patent_title] => 'Shallow trench isolation using antireflection layer' [patent_app_type] => utility [patent_app_number] => 10/972870 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4189 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/061/07061075.pdf [firstpage_image] =>[orig_patent_app_number] => 10972870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 404603 [patent_doc_number] => 07288432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Electronic devices with small functional elements supported on a carrier' [patent_app_type] => utility [patent_app_number] => 10/966617 [patent_app_country] => US [patent_app_date] => 2004-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 41 [patent_no_of_words] => 7467 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288432.pdf [firstpage_image] =>[orig_patent_app_number] => 10966617 [rel_patent_id] =>[rel_patent_doc_number] =>)