Search

Sue Hagarman

Examiner (ID: 2208)

Most Active Art Unit
3406
Art Unit(s)
3406
Total Applications
337
Issued Applications
322
Pending Applications
0
Abandoned Applications
15

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5649152 [patent_doc_number] => 20060134887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Method of manufacturing a slice of semiconductor' [patent_app_type] => utility [patent_app_number] => 10/545357 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1624 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20060134887.pdf [firstpage_image] =>[orig_patent_app_number] => 10545357 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/545357
Method of manufacturing a slice of semiconductor Feb 9, 2004 Abandoned
Array ( [id] => 5631781 [patent_doc_number] => 20060148251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Metal etching method for an interconnect structure and metal interconnect structure obtained by such method' [patent_app_type] => utility [patent_app_number] => 10/544607 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2490 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148251.pdf [firstpage_image] =>[orig_patent_app_number] => 10544607 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/544607
Metal etching method for an interconnect structure and metal interconnect structure obtained by such method Feb 2, 2004 Issued
Array ( [id] => 432660 [patent_doc_number] => 07265434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology' [patent_app_type] => utility [patent_app_number] => 10/767419 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 217 [patent_figures_cnt] => 276 [patent_no_of_words] => 34601 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/265/07265434.pdf [firstpage_image] =>[orig_patent_app_number] => 10767419 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/767419
Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology Jan 28, 2004 Issued
Array ( [id] => 7252987 [patent_doc_number] => 20040259318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology' [patent_app_type] => new [patent_app_number] => 10/767680 [patent_app_country] => US [patent_app_date] => 2004-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 220 [patent_figures_cnt] => 220 [patent_no_of_words] => 34841 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20040259318.pdf [firstpage_image] =>[orig_patent_app_number] => 10767680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/767680
Method of forming isolated pocket in a semiconductor substrate Jan 27, 2004 Issued
Array ( [id] => 495813 [patent_doc_number] => 07211863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology' [patent_app_type] => utility [patent_app_number] => 10/766774 [patent_app_country] => US [patent_app_date] => 2004-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 217 [patent_figures_cnt] => 272 [patent_no_of_words] => 34808 [patent_no_of_claims] => 175 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/211/07211863.pdf [firstpage_image] =>[orig_patent_app_number] => 10766774 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766774
Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology Jan 27, 2004 Issued
Array ( [id] => 485626 [patent_doc_number] => 07217641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates, and gallium nitride semiconductor structures fabricated thereby' [patent_app_type] => utility [patent_app_number] => 10/763588 [patent_app_country] => US [patent_app_date] => 2004-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 5729 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217641.pdf [firstpage_image] =>[orig_patent_app_number] => 10763588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/763588
Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates, and gallium nitride semiconductor structures fabricated thereby Jan 22, 2004 Issued
Array ( [id] => 508437 [patent_doc_number] => 07198970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Technique for perfecting the active regions of wide bandgap semiconductor nitride devices' [patent_app_type] => utility [patent_app_number] => 10/768747 [patent_app_country] => US [patent_app_date] => 2004-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3783 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/198/07198970.pdf [firstpage_image] =>[orig_patent_app_number] => 10768747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/768747
Technique for perfecting the active regions of wide bandgap semiconductor nitride devices Jan 22, 2004 Issued
Array ( [id] => 7436384 [patent_doc_number] => 20040230769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Method and device for producing layout patters of a semiconductor device having an even wafer surface' [patent_app_type] => new [patent_app_number] => 10/755387 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4321 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230769.pdf [firstpage_image] =>[orig_patent_app_number] => 10755387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/755387
Method and device for producing layout patterns of a semiconductor device having an even wafer surface Jan 12, 2004 Issued
Array ( [id] => 533789 [patent_doc_number] => 07176045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Laser diode operable in 1.3 μm or 1.5 μm wavelength band with improved efficiency' [patent_app_type] => utility [patent_app_number] => 10/753568 [patent_app_country] => US [patent_app_date] => 2004-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5477 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176045.pdf [firstpage_image] =>[orig_patent_app_number] => 10753568 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/753568
Laser diode operable in 1.3 μm or 1.5 μm wavelength band with improved efficiency Jan 8, 2004 Issued
Array ( [id] => 7324159 [patent_doc_number] => 20040137664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Advanced packaging shell for pocketable consumer electronic devices' [patent_app_type] => new [patent_app_number] => 10/751977 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3645 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137664.pdf [firstpage_image] =>[orig_patent_app_number] => 10751977 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/751977
Advanced packaging shell for pocketable consumer electronic devices Jan 6, 2004 Abandoned
Array ( [id] => 7319400 [patent_doc_number] => 20040135593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Fabrication method of semiconductor integrated circuit device and its testing apparatus' [patent_app_type] => new [patent_app_number] => 10/751937 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11491 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135593.pdf [firstpage_image] =>[orig_patent_app_number] => 10751937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/751937
Fabrication method of semiconductor integrated circuit device and its testing apparatus Jan 6, 2004 Abandoned
Array ( [id] => 7074858 [patent_doc_number] => 20050148126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Low voltage CMOS structure with dynamic threshold voltage' [patent_app_type] => utility [patent_app_number] => 10/752267 [patent_app_country] => US [patent_app_date] => 2004-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3766 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148126.pdf [firstpage_image] =>[orig_patent_app_number] => 10752267 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752267
Low voltage CMOS structure with dynamic threshold voltage Jan 5, 2004 Issued
Array ( [id] => 7074850 [patent_doc_number] => 20050148118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Horizontal TRAM and method for the fabrication thereof' [patent_app_type] => utility [patent_app_number] => 10/752357 [patent_app_country] => US [patent_app_date] => 2004-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20050148118.pdf [firstpage_image] =>[orig_patent_app_number] => 10752357 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752357
Horizontal TRAM and method for the fabrication thereof Jan 4, 2004 Issued
Array ( [id] => 843477 [patent_doc_number] => 07387922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Laser irradiation method, method for manufacturing semiconductor device, and laser irradiation system' [patent_app_type] => utility [patent_app_number] => 10/749505 [patent_app_country] => US [patent_app_date] => 2004-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6730 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/387/07387922.pdf [firstpage_image] =>[orig_patent_app_number] => 10749505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/749505
Laser irradiation method, method for manufacturing semiconductor device, and laser irradiation system Jan 1, 2004 Issued
Array ( [id] => 7154448 [patent_doc_number] => 20050082626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Membrane 3D IC fabrication' [patent_app_type] => utility [patent_app_number] => 10/741647 [patent_app_country] => US [patent_app_date] => 2003-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 65 [patent_no_of_words] => 26931 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20050082626.pdf [firstpage_image] =>[orig_patent_app_number] => 10741647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/741647
Membrane 3D IC fabrication Dec 17, 2003 Issued
Array ( [id] => 7301266 [patent_doc_number] => 20040113243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'UV cured polymeric semiconductor die coating' [patent_app_type] => new [patent_app_number] => 10/727947 [patent_app_country] => US [patent_app_date] => 2003-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1784 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113243.pdf [firstpage_image] =>[orig_patent_app_number] => 10727947 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/727947
UV cured polymeric semiconductor die coating Dec 2, 2003 Abandoned
Array ( [id] => 443678 [patent_doc_number] => 07256455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Double gate semiconductor device having a metal gate' [patent_app_type] => utility [patent_app_number] => 10/720166 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 3835 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256455.pdf [firstpage_image] =>[orig_patent_app_number] => 10720166 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/720166
Double gate semiconductor device having a metal gate Nov 24, 2003 Issued
Array ( [id] => 299816 [patent_doc_number] => 07538015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Method of manufacturing micro structure, and method of manufacturing mold material' [patent_app_type] => utility [patent_app_number] => 10/540637 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5309 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/538/07538015.pdf [firstpage_image] =>[orig_patent_app_number] => 10540637 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/540637
Method of manufacturing micro structure, and method of manufacturing mold material Nov 24, 2003 Issued
Array ( [id] => 7104034 [patent_doc_number] => 20050106760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method for increasing ferroelectric characteristics of polymer memory cells' [patent_app_type] => utility [patent_app_number] => 10/713307 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2219 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20050106760.pdf [firstpage_image] =>[orig_patent_app_number] => 10713307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713307
Method for increasing ferroelectric characteristics of polymer memory cells Nov 13, 2003 Issued
Array ( [id] => 7104108 [patent_doc_number] => 20050106834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method and apparatus for filling vias' [patent_app_type] => utility [patent_app_number] => 10/700327 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6632 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20050106834.pdf [firstpage_image] =>[orig_patent_app_number] => 10700327 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/700327
Method and apparatus for filling vias Nov 2, 2003 Issued
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