
Sue Hagarman
Examiner (ID: 2208)
| Most Active Art Unit | 3406 |
| Art Unit(s) | 3406 |
| Total Applications | 337 |
| Issued Applications | 322 |
| Pending Applications | 0 |
| Abandoned Applications | 15 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 461317
[patent_doc_number] => 07242075
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-10
[patent_title] => 'Silicon wafers and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/699438
[patent_app_country] => US
[patent_app_date] => 2003-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 27
[patent_no_of_words] => 9851
[patent_no_of_claims] => 15
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/242/07242075.pdf
[firstpage_image] =>[orig_patent_app_number] => 10699438
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/699438 | Silicon wafers and method of fabricating the same | Oct 30, 2003 | Issued |
Array
(
[id] => 6918282
[patent_doc_number] => 20050095843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Method for improving reliability of copper interconnects'
[patent_app_type] => utility
[patent_app_number] => 10/697137
[patent_app_country] => US
[patent_app_date] => 2003-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0095/20050095843.pdf
[firstpage_image] =>[orig_patent_app_number] => 10697137
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/697137 | Method for improving reliability of copper interconnects | Oct 29, 2003 | Issued |
Array
(
[id] => 6991045
[patent_doc_number] => 20050090082
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Method and system for improving performance of MOSFETs'
[patent_app_type] => utility
[patent_app_number] => 10/695307
[patent_app_country] => US
[patent_app_date] => 2003-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => publications/A1/0090/20050090082.pdf
[firstpage_image] =>[orig_patent_app_number] => 10695307
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/695307 | Method and system for improving performance of MOSFETs | Oct 27, 2003 | Abandoned |
Array
(
[id] => 7203513
[patent_doc_number] => 20040087055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Semiconductor device and method of making same'
[patent_app_type] => new
[patent_app_number] => 10/694687
[patent_app_country] => US
[patent_app_date] => 2003-10-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0087/20040087055.pdf
[firstpage_image] =>[orig_patent_app_number] => 10694687
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/694687 | Semiconductor device and method of making same | Oct 26, 2003 | Abandoned |
Array
(
[id] => 543666
[patent_doc_number] => 07163844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-16
[patent_title] => 'Monolithic common carrier'
[patent_app_type] => utility
[patent_app_number] => 10/692884
[patent_app_country] => US
[patent_app_date] => 2003-10-24
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/163/07163844.pdf
[firstpage_image] =>[orig_patent_app_number] => 10692884
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/692884 | Monolithic common carrier | Oct 23, 2003 | Issued |
Array
(
[id] => 7161985
[patent_doc_number] => 20050085047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'In situ hardmask pullback using an in situ plasma resist trim process'
[patent_app_type] => utility
[patent_app_number] => 10/689177
[patent_app_country] => US
[patent_app_date] => 2003-10-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0085/20050085047.pdf
[firstpage_image] =>[orig_patent_app_number] => 10689177
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/689177 | In situ hardmask pullback using an in situ plasma resist trim process | Oct 19, 2003 | Issued |
Array
(
[id] => 8209960
[patent_doc_number] => RE043450
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2012-06-05
[patent_title] => 'Method for fabricating semiconductor thin film'
[patent_app_type] => reissue
[patent_app_number] => 10/678139
[patent_app_country] => US
[patent_app_date] => 2003-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 8734
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/043/RE043450.pdf
[firstpage_image] =>[orig_patent_app_number] => 10678139
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/678139 | Method for fabricating semiconductor thin film | Oct 5, 2003 | Issued |
Array
(
[id] => 7433457
[patent_doc_number] => 20040065888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-08
[patent_title] => 'Vertical-cavity, surface-emission type laser diode and fabrication process thereof'
[patent_app_type] => new
[patent_app_number] => 10/677065
[patent_app_country] => US
[patent_app_date] => 2003-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 22850
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20040065888.pdf
[firstpage_image] =>[orig_patent_app_number] => 10677065
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677065 | Vertical-cavity, surface-emission type laser diode and fabrication process thereof | Sep 30, 2003 | Issued |
Array
(
[id] => 6931281
[patent_doc_number] => 20050282316
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Method of manufacturing an electronic device comprising a thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 10/529117
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => publications/A1/0282/20050282316.pdf
[firstpage_image] =>[orig_patent_app_number] => 10529117
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/529117 | Method of manufacturing an electronic device comprising a thin film transistor | Sep 11, 2003 | Issued |
Array
(
[id] => 982251
[patent_doc_number] => 06927095
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-09
[patent_title] => 'Low cost and compliant microelectronic packages for high I/O and fine pitch'
[patent_app_type] => utility
[patent_app_number] => 10/658177
[patent_app_country] => US
[patent_app_date] => 2003-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 6199
[patent_no_of_claims] => 28
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/927/06927095.pdf
[firstpage_image] =>[orig_patent_app_number] => 10658177
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/658177 | Low cost and compliant microelectronic packages for high I/O and fine pitch | Sep 8, 2003 | Issued |
Array
(
[id] => 7351123
[patent_doc_number] => 20040048202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-11
[patent_title] => 'Metal bump with an insulating sidewall and method of fabricating thereof'
[patent_app_type] => new
[patent_app_number] => 10/656248
[patent_app_country] => US
[patent_app_date] => 2003-09-08
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20040048202.pdf
[firstpage_image] =>[orig_patent_app_number] => 10656248
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/656248 | Metal bump with an insulating sidewall and method of fabricating thereof | Sep 7, 2003 | Issued |
Array
(
[id] => 996534
[patent_doc_number] => 06913973
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-05
[patent_title] => 'Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/653237
[patent_app_country] => US
[patent_app_date] => 2003-09-03
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[pdf_file] => patents/06/913/06913973.pdf
[firstpage_image] =>[orig_patent_app_number] => 10653237
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/653237 | Semiconductor device including transistor with composite gate structure and transistor with single gate structure, and method for manufacturing the same | Sep 2, 2003 | Issued |
Array
(
[id] => 7083297
[patent_doc_number] => 20050048677
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'THE USE OF A LAYOUT-OPTIMIZATION TOOL TO INCREASE THE YIELD AND RELIABILITY OF VLSI DESIGNS'
[patent_app_type] => utility
[patent_app_number] => 10/604987
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10604987
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604987 | THE USE OF A LAYOUT-OPTIMIZATION TOOL TO INCREASE THE YIELD AND RELIABILITY OF VLSI DESIGNS | Aug 28, 2003 | Abandoned |
Array
(
[id] => 1103370
[patent_doc_number] => 06811662
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-02
[patent_title] => 'Sputtering apparatus and manufacturing method of metal layer/metal compound layer by using thereof'
[patent_app_type] => B1
[patent_app_number] => 10/604857
[patent_app_country] => US
[patent_app_date] => 2003-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[pdf_file] => patents/06/811/06811662.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604857
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604857 | Sputtering apparatus and manufacturing method of metal layer/metal compound layer by using thereof | Aug 21, 2003 | Issued |
Array
(
[id] => 7203932
[patent_doc_number] => 20050042835
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Metal-insulator-metal capacitor and method of fabricating same'
[patent_app_type] => utility
[patent_app_number] => 10/643307
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[firstpage_image] =>[orig_patent_app_number] => 10643307
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/643307 | Metal-insulator-metal capacitor and method of fabricating same | Aug 18, 2003 | Issued |
Array
(
[id] => 759295
[patent_doc_number] => 07015546
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-21
[patent_title] => 'Deterministically doped field-effect devices and methods of making same'
[patent_app_type] => utility
[patent_app_number] => 10/604747
[patent_app_country] => US
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[pdf_file] => patents/07/015/07015546.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604747
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604747 | Deterministically doped field-effect devices and methods of making same | Aug 13, 2003 | Issued |
Array
(
[id] => 1027951
[patent_doc_number] => 06881667
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-19
[patent_title] => 'Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer'
[patent_app_type] => utility
[patent_app_number] => 10/637107
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/637107 | Low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer | Aug 7, 2003 | Issued |
Array
(
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[patent_issue_date] => 2008-04-22
[patent_title] => 'RF semiconductor devices and methods for fabricating the same'
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[firstpage_image] =>[orig_patent_app_number] => 10627057
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/627057 | RF semiconductor devices and methods for fabricating the same | Jul 24, 2003 | Issued |
Array
(
[id] => 963578
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[patent_issue_date] => 2005-09-27
[patent_title] => 'Method of fabricating liquid crystal display device'
[patent_app_type] => utility
[patent_app_number] => 10/621327
[patent_app_country] => US
[patent_app_date] => 2003-07-18
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[firstpage_image] =>[orig_patent_app_number] => 10621327
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/621327 | Method of fabricating liquid crystal display device | Jul 17, 2003 | Issued |
Array
(
[id] => 7221358
[patent_doc_number] => 20050260836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Method to overcome instability of ultra-shallow semiconductor junctions'
[patent_app_type] => utility
[patent_app_number] => 10/523127
[patent_app_country] => US
[patent_app_date] => 2003-07-17
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[firstpage_image] =>[orig_patent_app_number] => 10523127
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/523127 | Method to overcome instability of ultra-shallow semiconductor junctions | Jul 16, 2003 | Abandoned |