
Sue X. Lao
Examiner (ID: 7164)
| Most Active Art Unit | 2126 |
| Art Unit(s) | 2194, 2151, 2755, 2126 |
| Total Applications | 284 |
| Issued Applications | 211 |
| Pending Applications | 49 |
| Abandoned Applications | 24 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11567663
[patent_doc_number] => 20170106308
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-04-20
[patent_title] => 'Modular Block And Electronic Block System'
[patent_app_type] => utility
[patent_app_number] => 15/391596
[patent_app_country] => US
[patent_app_date] => 2016-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2709
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391596
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/391596 | Modular Block And Electronic Block System | Dec 26, 2016 | Abandoned |
Array
(
[id] => 12845476
[patent_doc_number] => 20180173665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-06-21
[patent_title] => HARD RESET OVER I3C BUS
[patent_app_type] => utility
[patent_app_number] => 15/382102
[patent_app_country] => US
[patent_app_date] => 2016-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15382102
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/382102 | HARD RESET OVER I3C BUS | Dec 15, 2016 | Abandoned |
Array
(
[id] => 17744447
[patent_doc_number] => 11392516
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Memory devices and methods having instruction acknowledgement
[patent_app_type] => utility
[patent_app_number] => 15/351390
[patent_app_country] => US
[patent_app_date] => 2016-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 10433
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351390
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/351390 | Memory devices and methods having instruction acknowledgement | Nov 13, 2016 | Issued |
Array
(
[id] => 11459019
[patent_doc_number] => 20170052925
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'Packet Data Processing Method, Apparatus, and System'
[patent_app_type] => utility
[patent_app_number] => 15/344972
[patent_app_country] => US
[patent_app_date] => 2016-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/344972 | Packet data processing method, apparatus, and system | Nov 6, 2016 | Issued |
Array
(
[id] => 17802128
[patent_doc_number] => 11416429
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-16
[patent_title] => Multi-functional PCI dummy card design
[patent_app_type] => utility
[patent_app_number] => 15/229532
[patent_app_country] => US
[patent_app_date] => 2016-08-05
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/229532 | Multi-functional PCI dummy card design | Aug 4, 2016 | Issued |
Array
(
[id] => 14766659
[patent_doc_number] => 10394726
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Network of memory modules with logarithmic access
[patent_app_type] => utility
[patent_app_number] => 15/229708
[patent_app_country] => US
[patent_app_date] => 2016-08-05
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15229708
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/229708 | Network of memory modules with logarithmic access | Aug 4, 2016 | Issued |
Array
(
[id] => 12180660
[patent_doc_number] => 20180039596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-08
[patent_title] => 'SUPPORTING INTERNAL RESISTIVE MEMORY FUNCTIONS USING A SERIAL PERIPHERAL INTERFACE (SPI)'
[patent_app_type] => utility
[patent_app_number] => 15/228975
[patent_app_country] => US
[patent_app_date] => 2016-08-04
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15228975
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/228975 | SUPPORTING INTERNAL RESISTIVE MEMORY FUNCTIONS USING A SERIAL PERIPHERAL INTERFACE (SPI) | Aug 3, 2016 | Abandoned |
Array
(
[id] => 16278740
[patent_doc_number] => 10761770
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-01
[patent_title] => Data management method and apparatus using buffering
[patent_app_type] => utility
[patent_app_number] => 15/186870
[patent_app_country] => US
[patent_app_date] => 2016-06-20
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/186870 | Data management method and apparatus using buffering | Jun 19, 2016 | Issued |
Array
(
[id] => 11352482
[patent_doc_number] => 20160371222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-22
[patent_title] => 'COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYER'
[patent_app_type] => utility
[patent_app_number] => 15/184181
[patent_app_country] => US
[patent_app_date] => 2016-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184181
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/184181 | COHERENCY DRIVEN ENHANCEMENTS TO A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS (PCIe) TRANSACTION LAYER | Jun 15, 2016 | Abandoned |
Array
(
[id] => 16644395
[patent_doc_number] => 10922252
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Extended message signaled interrupts (MSI) message data
[patent_app_type] => utility
[patent_app_number] => 15/184124
[patent_app_country] => US
[patent_app_date] => 2016-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184124
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/184124 | Extended message signaled interrupts (MSI) message data | Jun 15, 2016 | Issued |
Array
(
[id] => 15284719
[patent_doc_number] => 10515024
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-12-24
[patent_title] => Event generating unit
[patent_app_type] => utility
[patent_app_number] => 15/578665
[patent_app_country] => US
[patent_app_date] => 2016-05-06
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/578665 | Event generating unit | May 5, 2016 | Issued |
Array
(
[id] => 16065357
[patent_doc_number] => 10691628
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Systems and methods for flexible HDD/SSD storage support
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Array
(
[id] => 16232454
[patent_doc_number] => 10740002
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[patent_kind] => B1
[patent_issue_date] => 2020-08-11
[patent_title] => System status log
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Array
(
[id] => 11665278
[patent_doc_number] => 20170153997
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[patent_title] => 'BUS SYSTEM'
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Array
(
[id] => 16462909
[patent_doc_number] => 10846257
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[patent_kind] => B2
[patent_issue_date] => 2020-11-24
[patent_title] => Intelligent load balancing and high speed intelligent network recorders
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Array
(
[id] => 11397055
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[patent_title] => 'DATA PROCESSING SYSTEM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/144561 | Data processing system | May 1, 2016 | Issued |
Array
(
[id] => 14265079
[patent_doc_number] => 10282103
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[patent_kind] => B1
[patent_issue_date] => 2019-05-07
[patent_title] => Method and apparatus to delete a command queue
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Array
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[patent_issue_date] => 2020-02-25
[patent_title] => Method and apparatus to perform a function level reset in a memory controller
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Array
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[patent_title] => 'STORAGE SYSTEM THAT INCLUDES A PLURALITY OF ROUTING CIRCUITS AND A PLURALITY OF NODE MODULES CONNECTED THERETO'
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