Sue X. Lao

Array ( [id] => 19603331 [patent_doc_number] => 20240394211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SIGNAL TRANSMISSION METHOD AND ASSOCIATED HOST DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/661745 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19434715 [patent_doc_number] => 20240303213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => LOW COMPLEXITY ETHERNET NODE (LEN) ONE PORT [patent_app_type] => utility [patent_app_number] => 18/444090 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20160146 [patent_doc_number] => 12386775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => High speed passive serial configuration of FPGA by MCU using quad or octal SPI flash [patent_app_type] => utility [patent_app_number] => 18/440653 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20152234 [patent_doc_number] => 20250252072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => ENABLING OUT-OF-BAND GENERIC PCIE SWITCH CONTROL/CONFIGURATION MANAGEMENT USING BMC FOR DYNAMIC, SCALABLE HARDWARE REQUIREMENTS [patent_app_type] => utility [patent_app_number] => 18/433017 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19235924 [patent_doc_number] => 20240193119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => ELECTRONIC DEVICE FOR SETTING OPERATING MODE OF INTERFACE ON BASIS OF PERFORMANCE INFORMATION ABOUT EXTERNAL ELECTRONIC DEVICE, AND ELECTRONIC DEVICE OPERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/430034 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20070808 [patent_doc_number] => 20250209030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => DIGITAL OPEN PIN DETECTION [patent_app_type] => utility [patent_app_number] => 18/391980 [patent_app_country] => US [patent_app_date] => 2023-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18391980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19864754 [patent_doc_number] => 20250103540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => DETECTION OF A STOP CONDITION ASSERTED BY A TARGET ON A SERIAL DATA BUS [patent_app_type] => utility [patent_app_number] => 18/538689 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19864754 [patent_doc_number] => 20250103540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => DETECTION OF A STOP CONDITION ASSERTED BY A TARGET ON A SERIAL DATA BUS [patent_app_type] => utility [patent_app_number] => 18/538689 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19114961 [patent_doc_number] => 20240126711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => DETECTING AND HANDLING A COEXISTENCE EVENT [patent_app_type] => utility [patent_app_number] => 18/537065 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537065 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19069622 [patent_doc_number] => 20240104048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => Transmitting Apparatus, Receiving Apparatus, Parameter Adjustment Method, SerDes Circuit, and Electronic Device [patent_app_type] => utility [patent_app_number] => 18/526047 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11918 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19267714 [patent_doc_number] => 20240211417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => FAST MASS STORAGE ACCESS FOR DIGITAL COMPUTERS [patent_app_type] => utility [patent_app_number] => 18/526870 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19192261 [patent_doc_number] => 20240171174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => BACKPOWER-SAFE TEST SWITCH [patent_app_type] => utility [patent_app_number] => 18/511786 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18944615 [patent_doc_number] => 20240039754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => CIRCUIT BOARD, CONTROLLER ASSEMBLY, CONTROLLER, CONTROL METHOD, AND VEHICLE [patent_app_type] => utility [patent_app_number] => 18/486900 [patent_app_country] => US [patent_app_date] => 2023-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18486900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925540 [patent_doc_number] => 20240028544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => INTER-DIE COMMUNICATION OF PROGRAMMABLE LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/478003 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925540 [patent_doc_number] => 20240028544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => INTER-DIE COMMUNICATION OF PROGRAMMABLE LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/478003 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18478003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20344672 [patent_doc_number] => 12468402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Secured KVM switching device with unidirectional communications [patent_app_type] => utility [patent_app_number] => 18/372086 [patent_app_country] => US [patent_app_date] => 2023-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5989 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18372086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881326 [patent_doc_number] => 20240004695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => Method and Apparatus for Processing Interrupt Request [patent_app_type] => utility [patent_app_number] => 18/469069 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18881326 [patent_doc_number] => 20240004695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => Method and Apparatus for Processing Interrupt Request [patent_app_type] => utility [patent_app_number] => 18/469069 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20331607 [patent_doc_number] => 12461884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Serial interface receiver and offset calibration method thereof [patent_app_type] => utility [patent_app_number] => 18/458332 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3394 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19006038 [patent_doc_number] => 20240070109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => UNIVERSAL SERIAL BUS DEVICE AND SYSTEM TYPE DETERMINING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/453920 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453920 [rel_patent_id] =>[rel_patent_doc_number] =>)