
Sue X. Lao
Examiner (ID: 7164)
| Most Active Art Unit | 2126 |
| Art Unit(s) | 2194, 2151, 2755, 2126 |
| Total Applications | 284 |
| Issued Applications | 211 |
| Pending Applications | 49 |
| Abandoned Applications | 24 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19355636
[patent_doc_number] => 12056078
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-06
[patent_title] => Addressing multiphase power stage modules for power state and thermal management
[patent_app_type] => utility
[patent_app_number] => 17/815995
[patent_app_country] => US
[patent_app_date] => 2022-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8197
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815995
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/815995 | Addressing multiphase power stage modules for power state and thermal management | Jul 28, 2022 | Issued |
Array
(
[id] => 18022859
[patent_doc_number] => 20220374358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-24
[patent_title] => ADAPTIVE CREDIT-BASED REPLENISHMENT THRESHOLD USED FOR TRANSACTION ARBITRATION IN A SYSTEM THAT SUPPORTS MULTIPLE LEVELS OF CREDIT EXPENDITURE
[patent_app_type] => utility
[patent_app_number] => 17/875457
[patent_app_country] => US
[patent_app_date] => 2022-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25315
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875457
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/875457 | Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure | Jul 27, 2022 | Issued |
Array
(
[id] => 19092605
[patent_doc_number] => 11954054
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-09
[patent_title] => Communication system, slave unit used for communication system, and communication method
[patent_app_type] => utility
[patent_app_number] => 17/814302
[patent_app_country] => US
[patent_app_date] => 2022-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5497
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814302
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/814302 | Communication system, slave unit used for communication system, and communication method | Jul 21, 2022 | Issued |
Array
(
[id] => 17984724
[patent_doc_number] => 20220350761
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => MEMORY DEVICES AND METHODS HAVING MULTIPLE ACKNOWLEDGEMENTS IN RESPONSE TO A SAME INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 17/867638
[patent_app_country] => US
[patent_app_date] => 2022-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10448
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867638
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/867638 | Memory devices and methods having multiple acknowledgements in response to a same instruction | Jul 17, 2022 | Issued |
Array
(
[id] => 18981981
[patent_doc_number] => 11907154
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Latency and power efficient clock and data recovery in a high-speed one-wire bidirectional bus
[patent_app_type] => utility
[patent_app_number] => 17/861886
[patent_app_country] => US
[patent_app_date] => 2022-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 24193
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861886
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/861886 | Latency and power efficient clock and data recovery in a high-speed one-wire bidirectional bus | Jul 10, 2022 | Issued |
Array
(
[id] => 19275992
[patent_doc_number] => 12026120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Sharing high speed serial interconnects for different protocols
[patent_app_type] => utility
[patent_app_number] => 17/845717
[patent_app_country] => US
[patent_app_date] => 2022-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 7963
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845717
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/845717 | Sharing high speed serial interconnects for different protocols | Jun 20, 2022 | Issued |
Array
(
[id] => 19653289
[patent_doc_number] => 12175077
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Semiconductor storage device
[patent_app_type] => utility
[patent_app_number] => 17/806815
[patent_app_country] => US
[patent_app_date] => 2022-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 13061
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806815
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/806815 | Semiconductor storage device | Jun 13, 2022 | Issued |
Array
(
[id] => 19275991
[patent_doc_number] => 12026119
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Cryptocurrency miner and device enumeration
[patent_app_type] => utility
[patent_app_number] => 17/837810
[patent_app_country] => US
[patent_app_date] => 2022-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7904
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17837810
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/837810 | Cryptocurrency miner and device enumeration | Jun 9, 2022 | Issued |
Array
(
[id] => 18889530
[patent_doc_number] => 11868300
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-09
[patent_title] => Deferred communications over a synchronous interface
[patent_app_type] => utility
[patent_app_number] => 17/831856
[patent_app_country] => US
[patent_app_date] => 2022-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 15083
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831856
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/831856 | Deferred communications over a synchronous interface | Jun 2, 2022 | Issued |
Array
(
[id] => 18810874
[patent_doc_number] => 20230385210
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => Data Storage Device and Method for Lane Detection and Configuration
[patent_app_type] => utility
[patent_app_number] => 17/828334
[patent_app_country] => US
[patent_app_date] => 2022-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6822
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828334
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/828334 | Data storage device and method for lane detection and configuration | May 30, 2022 | Issued |
Array
(
[id] => 18644718
[patent_doc_number] => 11768786
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-26
[patent_title] => Connection interface conversion chip, connection interface conversion device and operation method
[patent_app_type] => utility
[patent_app_number] => 17/827804
[patent_app_country] => US
[patent_app_date] => 2022-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7998
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827804
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/827804 | Connection interface conversion chip, connection interface conversion device and operation method | May 29, 2022 | Issued |
Array
(
[id] => 19014730
[patent_doc_number] => 11921660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-05
[patent_title] => Equalization time configuration method, chip, and communications system
[patent_app_type] => utility
[patent_app_number] => 17/827271
[patent_app_country] => US
[patent_app_date] => 2022-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 18970
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827271
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/827271 | Equalization time configuration method, chip, and communications system | May 26, 2022 | Issued |
Array
(
[id] => 18855672
[patent_doc_number] => 11853251
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-26
[patent_title] => On-die chip-to-chip (C2C) link state monitor
[patent_app_type] => utility
[patent_app_number] => 17/662032
[patent_app_country] => US
[patent_app_date] => 2022-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9288
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662032
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/662032 | On-die chip-to-chip (C2C) link state monitor | May 3, 2022 | Issued |
Array
(
[id] => 18819665
[patent_doc_number] => 20230394005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => SERVER MANAGEMENT FRAMEWORK AND SERVER
[patent_app_type] => utility
[patent_app_number] => 18/270232
[patent_app_country] => US
[patent_app_date] => 2022-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3228
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18270232
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/270232 | Server management framework and server | Apr 25, 2022 | Issued |
Array
(
[id] => 17736735
[patent_doc_number] => 20220222194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-14
[patent_title] => ON-PACKAGE ACCELERATOR COMPLEX (AC) FOR INTEGRATING ACCELERATOR AND IOS FOR SCALABLE RAN AND EDGE CLOUD SOLUTION
[patent_app_type] => utility
[patent_app_number] => 17/711986
[patent_app_country] => US
[patent_app_date] => 2022-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7039
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17711986
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/711986 | ON-PACKAGE ACCELERATOR COMPLEX (AC) FOR INTEGRATING ACCELERATOR AND IOS FOR SCALABLE RAN AND EDGE CLOUD SOLUTION | Mar 31, 2022 | Pending |
Array
(
[id] => 20018134
[patent_doc_number] => 20250156356
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-15
[patent_title] => TECHNIQUES TO UTILIZE NEAR MEMORY COMPUTE CIRCUITRY FOR MEMORY-BOUND WORKLOADS
[patent_app_type] => utility
[patent_app_number] => 18/834582
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5855
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18834582
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/834582 | TECHNIQUES TO UTILIZE NEAR MEMORY COMPUTE CIRCUITRY FOR MEMORY-BOUND WORKLOADS | Mar 29, 2022 | Pending |
Array
(
[id] => 18659971
[patent_doc_number] => 20230305978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY
[patent_app_type] => utility
[patent_app_number] => 17/702271
[patent_app_country] => US
[patent_app_date] => 2022-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 35059
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702271
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/702271 | CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY | Mar 22, 2022 | Pending |
Array
(
[id] => 18659971
[patent_doc_number] => 20230305978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY
[patent_app_type] => utility
[patent_app_number] => 17/702271
[patent_app_country] => US
[patent_app_date] => 2022-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 35059
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17702271
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/702271 | CHIPLET ARCHITECTURE FOR LATE BIND SKU FUNGIBILITY | Mar 22, 2022 | Pending |
Array
(
[id] => 19280984
[patent_doc_number] => 20240217458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => VEHICLE MOUNTED COMMUNICATION APPARATUS AND VEHICLE MOUNTED COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/552004
[patent_app_country] => US
[patent_app_date] => 2022-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9328
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18552004
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/552004 | VEHICLE MOUNTED COMMUNICATION APPARATUS AND VEHICLE MOUNTED COMMUNICATION SYSTEM | Mar 7, 2022 | Pending |
Array
(
[id] => 17675083
[patent_doc_number] => 20220188250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-16
[patent_title] => MULTIPLE MEMORY TYPE SHARED MEMORY BUS SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 17/682908
[patent_app_country] => US
[patent_app_date] => 2022-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22467
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682908
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/682908 | Multiple memory type shared memory bus systems and methods | Feb 27, 2022 | Issued |