Sue X. Lao

Array ( [id] => 18599091 [patent_doc_number] => 20230273891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => CONTROL OF POWER USE OF A DEVICE POWERED BY A COMMUNICATION BUS AND DETERMINING SIDEBAND SIGNALING VOLTAGE LEVEL [patent_app_type] => utility [patent_app_number] => 17/680902 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17659356 [patent_doc_number] => 20220179821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => HARDWARE AND PROTOCOLS TO SUPPORT IMAGE TRANSFERS OVER MIPI I2C/I3C BUSES [patent_app_type] => utility [patent_app_number] => 17/680623 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18599091 [patent_doc_number] => 20230273891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => CONTROL OF POWER USE OF A DEVICE POWERED BY A COMMUNICATION BUS AND DETERMINING SIDEBAND SIGNALING VOLTAGE LEVEL [patent_app_type] => utility [patent_app_number] => 17/680902 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17643990 [patent_doc_number] => 20220171728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => METHOD FOR THE EMERGENCY SHUTDOWN OF A BUS SYSTEM, AND BUS SYSTEM [patent_app_type] => utility [patent_app_number] => 17/672129 [patent_app_country] => US [patent_app_date] => 2022-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17672129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18592143 [patent_doc_number] => 11741041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Interface bus resource allocation [patent_app_type] => utility [patent_app_number] => 17/668512 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 7253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17832341 [patent_doc_number] => 20220269645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => MEMORY MAT AS A REGISTER FILE [patent_app_type] => utility [patent_app_number] => 17/668260 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 113366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17794305 [patent_doc_number] => 20220253397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => METHODS FOR INTELLIGENT LOAD BALANCING AND HIGH SPEED INTELLIGENT NETWORK RECORDERS [patent_app_type] => utility [patent_app_number] => 17/585514 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18911804 [patent_doc_number] => 11874782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-16 [patent_title] => Fast mass storage access for digital computers [patent_app_type] => utility [patent_app_number] => 17/556419 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8128 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17763523 [patent_doc_number] => 20220237135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => USB 2.0 PHOTOELECTRIC TRANSMISSION SYSTEM [patent_app_type] => utility [patent_app_number] => 17/549841 [patent_app_country] => US [patent_app_date] => 2021-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18689097 [patent_doc_number] => 11784849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Communication control device for a user station for a serial bus system, and method for communicating in a serial bus system [patent_app_type] => utility [patent_app_number] => 17/457478 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8951 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18644726 [patent_doc_number] => 11768795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Thunderbolt device module and electronic device having root complex and integrating with such thunderbolt device module [patent_app_type] => utility [patent_app_number] => 17/539420 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3995 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18393504 [patent_doc_number] => 20230161724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => DETECTING AND HANDLING A COEXISTENCE EVENT [patent_app_type] => utility [patent_app_number] => 17/533046 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20304003 [patent_doc_number] => 12449990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Adjusting trim settings to improve memory performance or reliability [patent_app_type] => utility [patent_app_number] => 17/528579 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2382 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18378173 [patent_doc_number] => 20230153260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => PROTOCOL AWARE BRIDGE CIRCUIT FOR LOW LATENCY COMMUNICATION AMONG INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/455125 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19383183 [patent_doc_number] => 20240273053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SERIAL PORT CONTROL SYSTEM BASED ON COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD) AND COMMUNICATION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/569727 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18569727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17962256 [patent_doc_number] => 20220342837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/521624 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18734774 [patent_doc_number] => 11803506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => PCIe routing [patent_app_type] => utility [patent_app_number] => 17/512758 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3806 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17581282 [patent_doc_number] => 20220138137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => USB DEVICE REMOVAL AND PING INTERVENTION IN AN EXTENSION ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 17/512333 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18847102 [patent_doc_number] => 20230409506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => DATA TRANSMISSION METHOD, DEVICE, NETWORK SYSTEM, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/034357 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13838 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18034357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18248167 [patent_doc_number] => 11604756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => High-speed, out-of-band (OOB) management links for inter-baseboard management controller (BMC) communications in high performance computing (HPC) platforms [patent_app_type] => utility [patent_app_number] => 17/502303 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 13028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502303 [rel_patent_id] =>[rel_patent_doc_number] =>)