Search

Suian Tang

Examiner (ID: 496, Phone: (571)270-7404 , Office: P/2814 )

Most Active Art Unit
2814
Art Unit(s)
2814
Total Applications
629
Issued Applications
463
Pending Applications
1
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16332422 [patent_doc_number] => 20200303388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => STACKED VERTICAL TRANSISTOR ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND PROGRAMMABLE INVERTER DEVICES [patent_app_type] => utility [patent_app_number] => 16/359070 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16359070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/359070
Stacked vertical transistor erasable programmable read-only memory and programmable inverter devices Mar 19, 2019 Issued
Array ( [id] => 16464053 [patent_doc_number] => 10847412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Interconnect structure, interconnect layout structure, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/354157 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6601 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354157 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354157
Interconnect structure, interconnect layout structure, and manufacturing method thereof Mar 13, 2019 Issued
Array ( [id] => 17091068 [patent_doc_number] => 11119252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Solid-state imaging device, method of manufacturing the same, and electronic apparatus [patent_app_type] => utility [patent_app_number] => 16/353384 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6000 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353384 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/353384
Solid-state imaging device, method of manufacturing the same, and electronic apparatus Mar 13, 2019 Issued
Array ( [id] => 14509953 [patent_doc_number] => 20190198631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => MEMORY CELL STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/293159 [patent_app_country] => US [patent_app_date] => 2019-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16293159 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/293159
Memory cell structures Mar 4, 2019 Issued
Array ( [id] => 17048029 [patent_doc_number] => 11101219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements [patent_app_type] => utility [patent_app_number] => 16/258041 [patent_app_country] => US [patent_app_date] => 2019-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7232 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16258041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/258041
Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements Jan 24, 2019 Issued
Array ( [id] => 14350885 [patent_doc_number] => 20190157415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => High-K Film Apparatus and Method [patent_app_type] => utility [patent_app_number] => 16/241560 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241560 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241560
High-K film apparatus and method Jan 6, 2019 Issued
Array ( [id] => 15375861 [patent_doc_number] => 10529658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory [patent_app_type] => utility [patent_app_number] => 16/202493 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 11425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202493 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202493
Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory Nov 27, 2018 Issued
Array ( [id] => 17077933 [patent_doc_number] => 11114348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Hybrid high-voltage low-voltage FinFET device [patent_app_type] => utility [patent_app_number] => 16/177715 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3472 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177715
Hybrid high-voltage low-voltage FinFET device Oct 31, 2018 Issued
Array ( [id] => 16911375 [patent_doc_number] => 11043424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Increase the volume of epitaxy regions [patent_app_type] => utility [patent_app_number] => 16/177889 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177889 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177889
Increase the volume of epitaxy regions Oct 31, 2018 Issued
Array ( [id] => 14350745 [patent_doc_number] => 20190157345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => MRAM, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE INCLUDING THE MRAM [patent_app_type] => utility [patent_app_number] => 16/177999 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177999 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177999
MRAM, method of manufacturing the same, and electronic device including the MRAM Oct 31, 2018 Issued
Array ( [id] => 17047955 [patent_doc_number] => 11101145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Semiconductor device with dummy micro bumps between stacking dies to improve flowability of underfill material [patent_app_type] => utility [patent_app_number] => 16/177576 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6109 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177576 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177576
Semiconductor device with dummy micro bumps between stacking dies to improve flowability of underfill material Oct 31, 2018 Issued
Array ( [id] => 16987950 [patent_doc_number] => 11075133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Underfill structure for semiconductor packages and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/177637 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177637 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177637
Underfill structure for semiconductor packages and methods of forming the same Oct 31, 2018 Issued
Array ( [id] => 15093365 [patent_doc_number] => 20190341494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/177464 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4985 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177464 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177464
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Oct 31, 2018 Abandoned
Array ( [id] => 14238085 [patent_doc_number] => 20190131215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => Symmetric Input Circuitry for IC in Two-Pin Package [patent_app_type] => utility [patent_app_number] => 16/177473 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177473 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177473
Symmetric input circuitry for IC in two-pin package Oct 31, 2018 Issued
Array ( [id] => 15717631 [patent_doc_number] => 20200105583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 16/178073 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16178073 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/178073
Semiconductor device and method Oct 31, 2018 Issued
Array ( [id] => 16464019 [patent_doc_number] => 10847378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Semiconductor device and method for planarizing the same [patent_app_type] => utility [patent_app_number] => 16/177835 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2946 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177835
Semiconductor device and method for planarizing the same Oct 31, 2018 Issued
Array ( [id] => 16594075 [patent_doc_number] => 10903352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Manufacturing method of vertical GaN-based semiconductor device and vertical GaN-based semiconductor device [patent_app_type] => utility [patent_app_number] => 16/177434 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6656 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177434
Manufacturing method of vertical GaN-based semiconductor device and vertical GaN-based semiconductor device Oct 31, 2018 Issued
Array ( [id] => 16896408 [patent_doc_number] => 11037970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Semiconductor package structure and related methods [patent_app_type] => utility [patent_app_number] => 16/177697 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177697
Semiconductor package structure and related methods Oct 31, 2018 Issued
Array ( [id] => 16272343 [patent_doc_number] => 20200273831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => DRIVING CHIP AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/756976 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16756976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/756976
Driving chip and display device Oct 29, 2018 Issued
Array ( [id] => 13996081 [patent_doc_number] => 20190067198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => LOW RESISTANCE CONTACTS INCLUDING INTERMETALLIC ALLOY OF NICKEL, PLATINUM, TITANIUM, ALUMINUM AND TYPE IV SEMICONDUCTOR ELEMENTS [patent_app_type] => utility [patent_app_number] => 16/168092 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168092
Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements Oct 22, 2018 Issued
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