
Suian Tang
Examiner (ID: 496, Phone: (571)270-7404 , Office: P/2814 )
| Most Active Art Unit | 2814 |
| Art Unit(s) | 2814 |
| Total Applications | 629 |
| Issued Applications | 463 |
| Pending Applications | 1 |
| Abandoned Applications | 165 |
Applications
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|---|---|---|---|
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