Search

Sujatha R. Sharma

Examiner (ID: 16184, Phone: (571)272-7886 , Office: P/2648 )

Most Active Art Unit
2618
Art Unit(s)
2682, 2618, 2684, 2681, 2648
Total Applications
681
Issued Applications
515
Pending Applications
28
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 979519 [patent_doc_number] => 06930525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'Methods and apparatus for delay circuit' [patent_app_type] => utility [patent_app_number] => 10/167709 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5897 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930525.pdf [firstpage_image] =>[orig_patent_app_number] => 10167709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/167709
Methods and apparatus for delay circuit Jun 11, 2002 Issued
Array ( [id] => 7963579 [patent_doc_number] => 06680639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'Phase shifting arrangement for generating mutually orthogonal signals' [patent_app_type] => B1 [patent_app_number] => 10/048714 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2490 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680639.pdf [firstpage_image] =>[orig_patent_app_number] => 10048714 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/048714
Phase shifting arrangement for generating mutually orthogonal signals Jun 10, 2002 Issued
Array ( [id] => 6677160 [patent_doc_number] => 20030227300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Multiple asynchronous switching system' [patent_app_type] => new [patent_app_number] => 10/170077 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3891 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227300.pdf [firstpage_image] =>[orig_patent_app_number] => 10170077 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/170077
Multiple asynchronous switching system Jun 10, 2002 Issued
Array ( [id] => 6790395 [patent_doc_number] => 20030085739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit' [patent_app_type] => new [patent_app_number] => 10/166255 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5191 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20030085739.pdf [firstpage_image] =>[orig_patent_app_number] => 10166255 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/166255
Method of and apparatus for detecting difference between frequencies, and phase locked loop circuit Jun 10, 2002 Issued
Array ( [id] => 1331809 [patent_doc_number] => 06600355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Clock generator circuit providing an output clock signal from phased input clock signals' [patent_app_type] => B1 [patent_app_number] => 10/166908 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 14157 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600355.pdf [firstpage_image] =>[orig_patent_app_number] => 10166908 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/166908
Clock generator circuit providing an output clock signal from phased input clock signals Jun 9, 2002 Issued
Array ( [id] => 6645697 [patent_doc_number] => 20030007569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Wideband modulation' [patent_app_type] => new [patent_app_number] => 10/165604 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1560 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20030007569.pdf [firstpage_image] =>[orig_patent_app_number] => 10165604 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/165604
Wideband modulation Jun 6, 2002 Abandoned
Array ( [id] => 6678708 [patent_doc_number] => 20030228849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Dual frequency voltage controlled oscillator circuit' [patent_app_type] => new [patent_app_number] => 10/163003 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1892 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20030228849.pdf [firstpage_image] =>[orig_patent_app_number] => 10163003 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163003
Dual frequency voltage controlled oscillator circuit Jun 5, 2002 Issued
Array ( [id] => 6677168 [patent_doc_number] => 20030227308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Delay locked loop circuit with time delay quantifier and control' [patent_app_type] => new [patent_app_number] => 10/164735 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4099 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227308.pdf [firstpage_image] =>[orig_patent_app_number] => 10164735 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164735
Delay locked loop circuit with time delay quantifier and control Jun 5, 2002 Issued
Array ( [id] => 1171295 [patent_doc_number] => 06756833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Delayed signal generation circuit' [patent_app_type] => B2 [patent_app_number] => 10/162074 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5538 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756833.pdf [firstpage_image] =>[orig_patent_app_number] => 10162074 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162074
Delayed signal generation circuit Jun 4, 2002 Issued
Array ( [id] => 1226195 [patent_doc_number] => 06700414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same' [patent_app_type] => B2 [patent_app_number] => 10/159260 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5529 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700414.pdf [firstpage_image] =>[orig_patent_app_number] => 10159260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159260
Phase comparator accurately comparing phases of two clock signals and clock generation circuit employing the same Jun 2, 2002 Issued
Array ( [id] => 1329475 [patent_doc_number] => 06603347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Amplifier having controllable input impedance' [patent_app_type] => B2 [patent_app_number] => 10/158915 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3256 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603347.pdf [firstpage_image] =>[orig_patent_app_number] => 10158915 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/158915
Amplifier having controllable input impedance Jun 2, 2002 Issued
Array ( [id] => 1267106 [patent_doc_number] => 06661271 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Multi-phase edge rate control for SCSI LVD' [patent_app_type] => B1 [patent_app_number] => 10/158613 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2388 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661271.pdf [firstpage_image] =>[orig_patent_app_number] => 10158613 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/158613
Multi-phase edge rate control for SCSI LVD May 29, 2002 Issued
Array ( [id] => 6699815 [patent_doc_number] => 20030222695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'System and method for distributing a reference clock in an integrated circuit using filtered power supply line' [patent_app_type] => new [patent_app_number] => 10/159584 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3987 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20030222695.pdf [firstpage_image] =>[orig_patent_app_number] => 10159584 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159584
System and method for distributing a reference clock in an integrated circuit using filtered power supply line May 29, 2002 Issued
Array ( [id] => 1285592 [patent_doc_number] => 06642761 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Interface circuit of various clock period between a fast slope signal and a very slow slope, voltage controlled delay cell' [patent_app_type] => B1 [patent_app_number] => 10/158466 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1898 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642761.pdf [firstpage_image] =>[orig_patent_app_number] => 10158466 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/158466
Interface circuit of various clock period between a fast slope signal and a very slow slope, voltage controlled delay cell May 29, 2002 Issued
Array ( [id] => 1182888 [patent_doc_number] => 06741110 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Method and/or circuit for generating precision programmable multiple phase angle clocks' [patent_app_type] => B2 [patent_app_number] => 10/156360 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741110.pdf [firstpage_image] =>[orig_patent_app_number] => 10156360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/156360
Method and/or circuit for generating precision programmable multiple phase angle clocks May 27, 2002 Issued
Array ( [id] => 6154704 [patent_doc_number] => 20020145457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'PLL device and programmable frequency-division device' [patent_app_type] => new [patent_app_number] => 10/155187 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 30311 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145457.pdf [firstpage_image] =>[orig_patent_app_number] => 10155187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155187
PLL device and programmable frequency-division device May 23, 2002 Abandoned
Array ( [id] => 6687549 [patent_doc_number] => 20030031272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Communication device and communication method ' [patent_app_type] => new [patent_app_number] => 10/130997 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12240 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20030031272.pdf [firstpage_image] =>[orig_patent_app_number] => 10130997 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/130997
Multi-carrier modulation and demodulation system using a half-symbolized symbol May 23, 2002 Issued
Array ( [id] => 6781495 [patent_doc_number] => 20030062942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Input circuit and semiconductor integrated circuit having the input circuit' [patent_app_type] => new [patent_app_number] => 10/152614 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 13229 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062942.pdf [firstpage_image] =>[orig_patent_app_number] => 10152614 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152614
Input circuit and semiconductor integrated circuit having the input circuit May 22, 2002 Issued
Array ( [id] => 1151908 [patent_doc_number] => 06774689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Triple input phase detector and methodology for setting delay between two sets of phase outputs' [patent_app_type] => B1 [patent_app_number] => 10/154031 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8573 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774689.pdf [firstpage_image] =>[orig_patent_app_number] => 10154031 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154031
Triple input phase detector and methodology for setting delay between two sets of phase outputs May 22, 2002 Issued
Array ( [id] => 6448165 [patent_doc_number] => 20020149430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Method and device for frequency synthesis using a phase locked loop' [patent_app_type] => new [patent_app_number] => 10/069444 [patent_app_country] => US [patent_app_date] => 2002-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1738 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149430.pdf [firstpage_image] =>[orig_patent_app_number] => 10069444 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/069444
Method and device for frequency synthesis using a phase locked loop May 21, 2002 Issued
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