Search

Sujatha R. Sharma

Examiner (ID: 16184, Phone: (571)272-7886 , Office: P/2648 )

Most Active Art Unit
2618
Art Unit(s)
2682, 2618, 2684, 2681, 2648
Total Applications
681
Issued Applications
515
Pending Applications
28
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1146223 [patent_doc_number] => 06778001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Semiconductor circuit components for supplying power to a load' [patent_app_type] => B2 [patent_app_number] => 10/058306 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 10512 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/778/06778001.pdf [firstpage_image] =>[orig_patent_app_number] => 10058306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058306
Semiconductor circuit components for supplying power to a load Jan 29, 2002 Issued
Array ( [id] => 6764334 [patent_doc_number] => 20030098732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Device for controlling clock signal phase to reduce clock skew' [patent_app_type] => new [patent_app_number] => 10/058392 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2294 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20030098732.pdf [firstpage_image] =>[orig_patent_app_number] => 10058392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058392
Device for controlling clock signal phase to reduce clock skew Jan 27, 2002 Issued
Array ( [id] => 6786089 [patent_doc_number] => 20030137328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Multiple VCO phase lock loop architecture' [patent_app_type] => new [patent_app_number] => 10/052264 [patent_app_country] => US [patent_app_date] => 2002-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5253 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20030137328.pdf [firstpage_image] =>[orig_patent_app_number] => 10052264 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052264
Multiple VCO phase lock loop architecture Jan 22, 2002 Issued
Array ( [id] => 1423306 [patent_doc_number] => 06522184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Flip-flop circuit' [patent_app_type] => B2 [patent_app_number] => 10/052554 [patent_app_country] => US [patent_app_date] => 2002-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 12198 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522184.pdf [firstpage_image] =>[orig_patent_app_number] => 10052554 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/052554
Flip-flop circuit Jan 22, 2002 Issued
Array ( [id] => 1285553 [patent_doc_number] => 06642754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Clock signal generator employing a DDS circuit' [patent_app_type] => B1 [patent_app_number] => 10/031682 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3091 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642754.pdf [firstpage_image] =>[orig_patent_app_number] => 10031682 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/031682
Clock signal generator employing a DDS circuit Jan 21, 2002 Issued
Array ( [id] => 1289625 [patent_doc_number] => 06639441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Clock signal correction circuit and semiconductor device implementing the same' [patent_app_type] => B2 [patent_app_number] => 10/046186 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8483 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639441.pdf [firstpage_image] =>[orig_patent_app_number] => 10046186 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/046186
Clock signal correction circuit and semiconductor device implementing the same Jan 15, 2002 Issued
Array ( [id] => 1106856 [patent_doc_number] => 06812754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Clock synchronizer with offset prevention function against variation of output potential of loop filter' [patent_app_type] => B1 [patent_app_number] => 10/030687 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 12057 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812754.pdf [firstpage_image] =>[orig_patent_app_number] => 10030687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/030687
Clock synchronizer with offset prevention function against variation of output potential of loop filter Jan 13, 2002 Issued
Array ( [id] => 1230418 [patent_doc_number] => 06696875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Pulse clock/signal delay apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/936963 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10782 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696875.pdf [firstpage_image] =>[orig_patent_app_number] => 09936963 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/936963
Pulse clock/signal delay apparatus and method Jan 6, 2002 Issued
Array ( [id] => 1179679 [patent_doc_number] => 06747495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Low jitter analog-digital locker loop with lock detection circuit' [patent_app_type] => B1 [patent_app_number] => 09/889260 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2003 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747495.pdf [firstpage_image] =>[orig_patent_app_number] => 09889260 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/889260
Low jitter analog-digital locker loop with lock detection circuit Jan 2, 2002 Issued
Array ( [id] => 5901984 [patent_doc_number] => 20020140486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'MULTIPHASE CLOCK GENERATOR' [patent_app_type] => new [patent_app_number] => 09/996043 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4648 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20020140486.pdf [firstpage_image] =>[orig_patent_app_number] => 09996043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996043
Multiphase clock generator Nov 27, 2001 Issued
Array ( [id] => 7355541 [patent_doc_number] => 20040090250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Phase regulating circuit a time-delay element' [patent_app_type] => new [patent_app_number] => 10/416618 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3152 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090250.pdf [firstpage_image] =>[orig_patent_app_number] => 10416618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/416618
Phase regulating circuit with a time-delay element Nov 20, 2001 Issued
Array ( [id] => 6799818 [patent_doc_number] => 20030094982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Core sync module' [patent_app_type] => new [patent_app_number] => 09/989315 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6844 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094982.pdf [firstpage_image] =>[orig_patent_app_number] => 09989315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/989315
Stratum clock state machine multiplexer switching Nov 19, 2001 Issued
Array ( [id] => 7436352 [patent_doc_number] => 20040066219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Radio transceiver having a phase-locked loop circuit' [patent_app_type] => new [patent_app_number] => 10/433745 [patent_app_country] => US [patent_app_date] => 2003-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4653 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20040066219.pdf [firstpage_image] =>[orig_patent_app_number] => 10433745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/433745
Radio transceiver having a phase-locked loop circuit Nov 14, 2001 Issued
Array ( [id] => 1413641 [patent_doc_number] => 06535049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Multipurpose test chip input/output circuit' [patent_app_type] => B2 [patent_app_number] => 09/992907 [patent_app_country] => US [patent_app_date] => 2001-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4641 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535049.pdf [firstpage_image] =>[orig_patent_app_number] => 09992907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992907
Multipurpose test chip input/output circuit Nov 13, 2001 Issued
Array ( [id] => 1530008 [patent_doc_number] => 06480036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Settable digital CMOS differential sense amplifier' [patent_app_type] => B2 [patent_app_number] => 09/992850 [patent_app_country] => US [patent_app_date] => 2001-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6335 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480036.pdf [firstpage_image] =>[orig_patent_app_number] => 09992850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992850
Settable digital CMOS differential sense amplifier Nov 11, 2001 Issued
Array ( [id] => 1576907 [patent_doc_number] => 06469559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'System and method for eliminating pulse width variations in digital delay lines' [patent_app_type] => B2 [patent_app_number] => 10/007875 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2955 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469559.pdf [firstpage_image] =>[orig_patent_app_number] => 10007875 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007875
System and method for eliminating pulse width variations in digital delay lines Nov 7, 2001 Issued
Array ( [id] => 1222457 [patent_doc_number] => 06703880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Generator for the production of clock signals' [patent_app_type] => B1 [patent_app_number] => 10/013343 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 5780 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703880.pdf [firstpage_image] =>[orig_patent_app_number] => 10013343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/013343
Generator for the production of clock signals Oct 29, 2001 Issued
Array ( [id] => 1377890 [patent_doc_number] => 06566925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Duty-cycle regulator' [patent_app_type] => B2 [patent_app_number] => 09/978905 [patent_app_country] => US [patent_app_date] => 2001-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4447 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566925.pdf [firstpage_image] =>[orig_patent_app_number] => 09978905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978905
Duty-cycle regulator Oct 17, 2001 Issued
Array ( [id] => 5918718 [patent_doc_number] => 20020113638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Termination resistor circuit for achieving highly versatile interface circuit and signal transmission system having the termination resistor circuit' [patent_app_type] => new [patent_app_number] => 09/978018 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6141 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113638.pdf [firstpage_image] =>[orig_patent_app_number] => 09978018 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978018
Termination resistor circuit for achieving highly versatile interface circuit and signal transmission system having the termination resistor circuit Oct 16, 2001 Abandoned
Array ( [id] => 1338355 [patent_doc_number] => 06597222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Power down circuit for high output impedance state of I/O driver' [patent_app_type] => B2 [patent_app_number] => 09/978255 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1409 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597222.pdf [firstpage_image] =>[orig_patent_app_number] => 09978255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978255
Power down circuit for high output impedance state of I/O driver Oct 14, 2001 Issued
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