Sujatha R. Sharma

Array ( [id] => 6579971 [patent_doc_number] => 20020041196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Delay locked loop' [patent_app_type] => new [patent_app_number] => 09/907267 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5559 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20020041196.pdf [firstpage_image] =>[orig_patent_app_number] => 09907267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1237637 [patent_doc_number] => 06690214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'DLL circuit and DLL control method' [patent_app_type] => B2 [patent_app_number] => 09/904035 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 11519 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/690/06690214.pdf [firstpage_image] =>[orig_patent_app_number] => 09904035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6206009 [patent_doc_number] => 20020070785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Clock signal generator' [patent_app_type] => new [patent_app_number] => 09/898919 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4658 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070785.pdf [firstpage_image] =>[orig_patent_app_number] => 09898919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1301180 [patent_doc_number] => 06628156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Integrated circuit having a timing circuit, and method for adjustment of an output signal from the timing circuit' [patent_app_type] => B2 [patent_app_number] => 09/897281 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4494 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/628/06628156.pdf [firstpage_image] =>[orig_patent_app_number] => 09897281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6222302 [patent_doc_number] => 20020003442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Reset circuit of semiconductor circuit' [patent_app_type] => new [patent_app_number] => 09/894840 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6484 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20020003442.pdf [firstpage_image] =>[orig_patent_app_number] => 09894840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1476844 [patent_doc_number] => 06388477 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Switchable voltage follower and bridge driver using the same' [patent_app_type] => B1 [patent_app_number] => 09/892763 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3230 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388477.pdf [firstpage_image] =>[orig_patent_app_number] => 09892763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424121 [patent_doc_number] => 06518802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Circuits and methods for generating an accurate digital representation of a sinusoidal wave' [patent_app_type] => B1 [patent_app_number] => 09/893054 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3460 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518802.pdf [firstpage_image] =>[orig_patent_app_number] => 09893054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1237656 [patent_doc_number] => 06690224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Architecture of a PLL with dynamic frequency control on a PLD' [patent_app_type] => B1 [patent_app_number] => 09/893161 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4068 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/690/06690224.pdf [firstpage_image] =>[orig_patent_app_number] => 09893161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6881857 [patent_doc_number] => 20010048329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'PLL device and programmable frequency-division device' [patent_app_type] => new [patent_app_number] => 09/888175 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 30141 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048329.pdf [firstpage_image] =>[orig_patent_app_number] => 09888175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6461911 [patent_doc_number] => 20020021150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Load drive circuit' [patent_app_type] => new [patent_app_number] => 09/884919 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8647 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021150.pdf [firstpage_image] =>[orig_patent_app_number] => 09884919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1315824 [patent_doc_number] => 06614291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Low voltage, high speed CMOS CML latch and MUX devices' [patent_app_type] => B1 [patent_app_number] => 09/881950 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4238 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614291.pdf [firstpage_image] =>[orig_patent_app_number] => 09881950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6238404 [patent_doc_number] => 20020044006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Fuse circuit for semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/879637 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2909 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20020044006.pdf [firstpage_image] =>[orig_patent_app_number] => 09879637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6510937 [patent_doc_number] => 20020135403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Trigger circuit' [patent_app_type] => new [patent_app_number] => 09/873789 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 43422 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20020135403.pdf [firstpage_image] =>[orig_patent_app_number] => 09873789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6335447 [patent_doc_number] => 20020033724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'Ladder type clock network for reducing skew of clock signals' [patent_app_type] => new [patent_app_number] => 09/864190 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2439 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20020033724.pdf [firstpage_image] =>[orig_patent_app_number] => 09864190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6270828 [patent_doc_number] => 20020105369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Clock buffer with DC offset suppression' [patent_app_type] => new [patent_app_number] => 09/865008 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1940 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105369.pdf [firstpage_image] =>[orig_patent_app_number] => 09865008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1413741 [patent_doc_number] => 06535057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Programmable glitch filter' [patent_app_type] => B2 [patent_app_number] => 09/864946 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 3478 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535057.pdf [firstpage_image] =>[orig_patent_app_number] => 09864946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 767580 [patent_doc_number] => 07009446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Active filter circuit with reduced noise' [patent_app_type] => utility [patent_app_number] => 09/860457 [patent_app_country] => US [patent_app_date] => 2001-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8799 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/009/07009446.pdf [firstpage_image] =>[orig_patent_app_number] => 09860457 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1292082 [patent_doc_number] => 06633184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Phase comparator and synchronizing signal extracting device' [patent_app_type] => B2 [patent_app_number] => 09/859505 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 42 [patent_no_of_words] => 19270 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633184.pdf [firstpage_image] =>[orig_patent_app_number] => 09859505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1591773 [patent_doc_number] => 06483361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Lock detector for determining phase lock condition in PLL on a period-by-period basis according to desired phase error' [patent_app_type] => B1 [patent_app_number] => 09/860966 [patent_app_country] => US [patent_app_date] => 2001-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4696 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483361.pdf [firstpage_image] =>[orig_patent_app_number] => 09860966 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5799154 [patent_doc_number] => 20020008557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Reduced jitter phase lock loop using a technique multi-stage digital delay line' [patent_app_type] => new [patent_app_number] => 09/858543 [patent_app_country] => US [patent_app_date] => 2001-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6570 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008557.pdf [firstpage_image] =>[orig_patent_app_number] => 09858543 [rel_patent_id] =>[rel_patent_doc_number] =>)