Search

Sujatha R. Sharma

Examiner (ID: 16184, Phone: (571)272-7886 , Office: P/2648 )

Most Active Art Unit
2618
Art Unit(s)
2682, 2618, 2684, 2681, 2648
Total Applications
681
Issued Applications
515
Pending Applications
28
Abandoned Applications
142

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1562566 [patent_doc_number] => 06437621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Waveform shaping device' [patent_app_type] => B2 [patent_app_number] => 09/816100 [patent_app_country] => US [patent_app_date] => 2001-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3513 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437621.pdf [firstpage_image] =>[orig_patent_app_number] => 09816100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/816100
Waveform shaping device Mar 25, 2001 Issued
Array ( [id] => 6066522 [patent_doc_number] => 20020032897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Method of designing wiring for power sources in a semiconductor chip, and a computer product' [patent_app_type] => new [patent_app_number] => 09/812552 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5436 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20020032897.pdf [firstpage_image] =>[orig_patent_app_number] => 09812552 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812552
Method of designing wiring for power sources in a semiconductor chip, and a computer product Mar 20, 2001 Issued
Array ( [id] => 5871747 [patent_doc_number] => 20020047731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Potential detecting circuit' [patent_app_type] => new [patent_app_number] => 09/809212 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7816 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047731.pdf [firstpage_image] =>[orig_patent_app_number] => 09809212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809212
Potential detecting circuit having wide operating margin and semiconductor device including the same Mar 15, 2001 Issued
Array ( [id] => 5840964 [patent_doc_number] => 20020130691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Method and apparatus for fast lock of delay lock loop' [patent_app_type] => new [patent_app_number] => 09/809717 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4908 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20020130691.pdf [firstpage_image] =>[orig_patent_app_number] => 09809717 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809717
Method and apparatus for fast lock of delay lock loop Mar 14, 2001 Abandoned
Array ( [id] => 7077235 [patent_doc_number] => 20010040479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Electronic switch' [patent_app_type] => new [patent_app_number] => 09/798326 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3318 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040479.pdf [firstpage_image] =>[orig_patent_app_number] => 09798326 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798326
Electronic switch Mar 1, 2001 Abandoned
Array ( [id] => 1456196 [patent_doc_number] => 06462585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'High performance CPL double-gate latch' [patent_app_type] => B1 [patent_app_number] => 09/788924 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2085 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462585.pdf [firstpage_image] =>[orig_patent_app_number] => 09788924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788924
High performance CPL double-gate latch Feb 19, 2001 Issued
Array ( [id] => 1203868 [patent_doc_number] => 06720817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-13 [patent_title] => 'All NPN class-AB log-domain integrator with supporting input and output circuitry for low-voltage and high-frequency continuous-time filtering' [patent_app_type] => B2 [patent_app_number] => 09/777939 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 8957 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 522 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720817.pdf [firstpage_image] =>[orig_patent_app_number] => 09777939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777939
All NPN class-AB log-domain integrator with supporting input and output circuitry for low-voltage and high-frequency continuous-time filtering Feb 6, 2001 Issued
Array ( [id] => 1562547 [patent_doc_number] => 06437617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of controlling a clock signal and circuit for controlling a clock signal' [patent_app_type] => B2 [patent_app_number] => 09/777331 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 35 [patent_no_of_words] => 16042 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437617.pdf [firstpage_image] =>[orig_patent_app_number] => 09777331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777331
Method of controlling a clock signal and circuit for controlling a clock signal Feb 5, 2001 Issued
Array ( [id] => 1544939 [patent_doc_number] => 06373308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Direct-measured DLL circuit and method' [patent_app_type] => B1 [patent_app_number] => 09/755671 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5950 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373308.pdf [firstpage_image] =>[orig_patent_app_number] => 09755671 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755671
Direct-measured DLL circuit and method Jan 4, 2001 Issued
Array ( [id] => 1544918 [patent_doc_number] => 06373300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Integrated circuit with multi-function controlled impedance output drivers' [patent_app_type] => B1 [patent_app_number] => 09/753966 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2549 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373300.pdf [firstpage_image] =>[orig_patent_app_number] => 09753966 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753966
Integrated circuit with multi-function controlled impedance output drivers Jan 1, 2001 Issued
Array ( [id] => 7040244 [patent_doc_number] => 20010005150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Latch type sense amplifier and method for operating thereof' [patent_app_type] => new-utility [patent_app_number] => 09/745428 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3120 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005150.pdf [firstpage_image] =>[orig_patent_app_number] => 09745428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745428
Latch type sense amplifier and method for operating thereof Dec 25, 2000 Abandoned
Array ( [id] => 6920777 [patent_doc_number] => 20010028262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Time interval measurement system incorporating a linear ramp generation circuit' [patent_app_type] => new [patent_app_number] => 09/747120 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4072 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028262.pdf [firstpage_image] =>[orig_patent_app_number] => 09747120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747120
Time interval measurement system incorporating a linear ramp generation circuit Dec 21, 2000 Abandoned
Array ( [id] => 951749 [patent_doc_number] => 06960954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Variable frequency electric signal generator, automatic control and low cost computing means' [patent_app_type] => utility [patent_app_number] => 10/168429 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6701 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960954.pdf [firstpage_image] =>[orig_patent_app_number] => 10168429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/168429
Variable frequency electric signal generator, automatic control and low cost computing means Dec 20, 2000 Issued
Array ( [id] => 1583688 [patent_doc_number] => 06424196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-23 [patent_title] => 'Secured master-slave D type flip-flop circuit' [patent_app_type] => B2 [patent_app_number] => 09/740269 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3647 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424196.pdf [firstpage_image] =>[orig_patent_app_number] => 09740269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/740269
Secured master-slave D type flip-flop circuit Dec 18, 2000 Issued
Array ( [id] => 1603431 [patent_doc_number] => 06433613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Translating switch circuit with disabling option' [patent_app_type] => B1 [patent_app_number] => 09/737977 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5449 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433613.pdf [firstpage_image] =>[orig_patent_app_number] => 09737977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737977
Translating switch circuit with disabling option Dec 14, 2000 Issued
Array ( [id] => 6124545 [patent_doc_number] => 20020075043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Push-pull amplifier for use in generating a reference voltage' [patent_app_type] => new [patent_app_number] => 09/734373 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1811 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20020075043.pdf [firstpage_image] =>[orig_patent_app_number] => 09734373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734373
Push-pull amplifier for use in generating a reference voltage Dec 13, 2000 Abandoned
Array ( [id] => 6205977 [patent_doc_number] => 20020070766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Signal detection scheme for data communication links' [patent_app_type] => new [patent_app_number] => 09/734794 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1288 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070766.pdf [firstpage_image] =>[orig_patent_app_number] => 09734794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/734794
Signal detection scheme for data communication links Dec 10, 2000 Abandoned
Array ( [id] => 6886014 [patent_doc_number] => 20010019283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'High-speed dynamic latch' [patent_app_type] => new [patent_app_number] => 09/731812 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2593 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019283.pdf [firstpage_image] =>[orig_patent_app_number] => 09731812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/731812
High-speed dynamic latch Dec 7, 2000 Abandoned
Array ( [id] => 6205975 [patent_doc_number] => 20020070764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Output driver circuit with current detection' [patent_app_type] => new [patent_app_number] => 09/733747 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2217 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070764.pdf [firstpage_image] =>[orig_patent_app_number] => 09733747 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733747
Output driver circuit with current detection Dec 7, 2000 Issued
Array ( [id] => 1345798 [patent_doc_number] => 06590433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Reduced power consumption bi-directional buffer' [patent_app_type] => B2 [patent_app_number] => 09/733445 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2904 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590433.pdf [firstpage_image] =>[orig_patent_app_number] => 09733445 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733445
Reduced power consumption bi-directional buffer Dec 7, 2000 Issued
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