
Sultana Begum
Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 635 |
| Issued Applications | 547 |
| Pending Applications | 72 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18615555
[patent_doc_number] => 20230282292
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => MEMORY DEVICE WITH HIGH CONTENT DENSITY
[patent_app_type] => utility
[patent_app_number] => 17/686469
[patent_app_country] => US
[patent_app_date] => 2022-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6985
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686469
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/686469 | Memory device with high content density | Mar 3, 2022 | Issued |
Array
(
[id] => 18379432
[patent_doc_number] => 20230154521
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/685054
[patent_app_country] => US
[patent_app_date] => 2022-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7461
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685054
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/685054 | Memory device and operating method for target refresh operation based on number of accesses | Mar 1, 2022 | Issued |
Array
(
[id] => 18256052
[patent_doc_number] => 20230083091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/684834
[patent_app_country] => US
[patent_app_date] => 2022-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10742
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684834
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/684834 | Semiconductor storage device and method of manufacturing semiconductor storage device | Mar 1, 2022 | Issued |
Array
(
[id] => 19183596
[patent_doc_number] => 11990192
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-21
[patent_title] => Integrated circuit with ESD protection
[patent_app_type] => utility
[patent_app_number] => 17/684190
[patent_app_country] => US
[patent_app_date] => 2022-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5825
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684190
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/684190 | Integrated circuit with ESD protection | Feb 28, 2022 | Issued |
Array
(
[id] => 18615542
[patent_doc_number] => 20230282279
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-07
[patent_title] => FILAMENT FORMING METHOD FOR RESISTIVE MEMORY UNIT
[patent_app_type] => utility
[patent_app_number] => 17/683356
[patent_app_country] => US
[patent_app_date] => 2022-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2997
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683356
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/683356 | Filament forming method for resistive memory unit | Feb 28, 2022 | Issued |
Array
(
[id] => 19107216
[patent_doc_number] => 11960319
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-16
[patent_title] => Memory device with real-time monitoring
[patent_app_type] => utility
[patent_app_number] => 17/678117
[patent_app_country] => US
[patent_app_date] => 2022-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 6299
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17678117
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/678117 | Memory device with real-time monitoring | Feb 22, 2022 | Issued |
Array
(
[id] => 18950739
[patent_doc_number] => 11894041
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => Electronic devices executing refresh operation based on adjusted internal voltage
[patent_app_type] => utility
[patent_app_number] => 17/676644
[patent_app_country] => US
[patent_app_date] => 2022-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 22227
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676644
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/676644 | Electronic devices executing refresh operation based on adjusted internal voltage | Feb 20, 2022 | Issued |
Array
(
[id] => 18585704
[patent_doc_number] => 20230267968
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-24
[patent_title] => TEMPERATURE-COMPENSATED TIME ESTIMATE FOR A BLOCK TO REACH A UNIFORM CHARGE LOSS STATE
[patent_app_type] => utility
[patent_app_number] => 17/675592
[patent_app_country] => US
[patent_app_date] => 2022-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10864
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675592
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/675592 | Temperature-compensated time estimate for a block to reach a uniform charge loss state | Feb 17, 2022 | Issued |
Array
(
[id] => 18548053
[patent_doc_number] => 11721411
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-08
[patent_title] => Method and device for testing memory chip by calculating resistance values
[patent_app_type] => utility
[patent_app_number] => 17/669520
[patent_app_country] => US
[patent_app_date] => 2022-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6028
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669520
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/669520 | Method and device for testing memory chip by calculating resistance values | Feb 10, 2022 | Issued |
Array
(
[id] => 17796458
[patent_doc_number] => 20220255550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-11
[patent_title] => INTEGRATED TRANSMITTER SLEW RATE CALIBRATION
[patent_app_type] => utility
[patent_app_number] => 17/590668
[patent_app_country] => US
[patent_app_date] => 2022-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6063
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17590668
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/590668 | Integrated transmitter slew rate calibration | Jan 31, 2022 | Issued |
Array
(
[id] => 17932967
[patent_doc_number] => 20220328093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => BITLINE SENSE AMPLIFIER AND A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/585865
[patent_app_country] => US
[patent_app_date] => 2022-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10516
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585865
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/585865 | Bitline sense amplifier and a memory device with an equalizer | Jan 26, 2022 | Issued |
Array
(
[id] => 18472703
[patent_doc_number] => 20230206991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => MEMORY DEVICE LAYOUT
[patent_app_type] => utility
[patent_app_number] => 17/584905
[patent_app_country] => US
[patent_app_date] => 2022-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5965
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584905
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/584905 | Memory device layout with intersecting region between sub-wordline and sense amplifier | Jan 25, 2022 | Issued |
Array
(
[id] => 18379439
[patent_doc_number] => 20230154528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-18
[patent_title] => DETERMINATION OF A BIAS VOLTAGE TO APPLY TO ONE OR MORE MEMORY CELLS IN A NEURAL NETWORK
[patent_app_type] => utility
[patent_app_number] => 17/585452
[patent_app_country] => US
[patent_app_date] => 2022-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15101
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585452
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/585452 | Determination of a bias voltage to apply to one or more memory cells in a neural network | Jan 25, 2022 | Issued |
Array
(
[id] => 19370307
[patent_doc_number] => 12062397
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Transceiver for providing high voltages for erase or program operations in a non-volatile memory system
[patent_app_type] => utility
[patent_app_number] => 17/585261
[patent_app_country] => US
[patent_app_date] => 2022-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 5022
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585261
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/585261 | Transceiver for providing high voltages for erase or program operations in a non-volatile memory system | Jan 25, 2022 | Issued |
Array
(
[id] => 18950761
[patent_doc_number] => 11894064
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-06
[patent_title] => Sub-block mode for non-volatile memory
[patent_app_type] => utility
[patent_app_number] => 17/583570
[patent_app_country] => US
[patent_app_date] => 2022-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 12444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583570
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/583570 | Sub-block mode for non-volatile memory | Jan 24, 2022 | Issued |
Array
(
[id] => 17917186
[patent_doc_number] => 20220319582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING MEMORY MANAGEMENT PROGRAM
[patent_app_type] => utility
[patent_app_number] => 17/582039
[patent_app_country] => US
[patent_app_date] => 2022-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10339
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582039
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/582039 | MEMORY MANAGEMENT APPARATUS, MEMORY MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING MEMORY MANAGEMENT PROGRAM | Jan 23, 2022 | Abandoned |
Array
(
[id] => 19316023
[patent_doc_number] => 12041860
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Resistive memory device and method for manufacturing with protrusion of electrode
[patent_app_type] => utility
[patent_app_number] => 17/581153
[patent_app_country] => US
[patent_app_date] => 2022-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6061
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581153
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/581153 | Resistive memory device and method for manufacturing with protrusion of electrode | Jan 20, 2022 | Issued |
Array
(
[id] => 19414501
[patent_doc_number] => 12080333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-03
[patent_title] => Semiconductor system for performing an active operation using an active period control method
[patent_app_type] => utility
[patent_app_number] => 17/577289
[patent_app_country] => US
[patent_app_date] => 2022-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 13943
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577289
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/577289 | Semiconductor system for performing an active operation using an active period control method | Jan 16, 2022 | Issued |
Array
(
[id] => 19426597
[patent_doc_number] => 12086015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Low power state implementation in a power management circuit
[patent_app_type] => utility
[patent_app_number] => 17/575334
[patent_app_country] => US
[patent_app_date] => 2022-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 6012
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575334
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/575334 | Low power state implementation in a power management circuit | Jan 12, 2022 | Issued |
Array
(
[id] => 19229414
[patent_doc_number] => 12009055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Far end driver for memory clock
[patent_app_type] => utility
[patent_app_number] => 17/571670
[patent_app_country] => US
[patent_app_date] => 2022-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7390
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571670
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/571670 | Far end driver for memory clock | Jan 9, 2022 | Issued |