Search

Sultana Begum

Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
635
Issued Applications
547
Pending Applications
72
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18047737 [patent_doc_number] => 11521695 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Digital bit generators for trim circuits [patent_app_type] => utility [patent_app_number] => 17/347236 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4234 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347236
Digital bit generators for trim circuits Jun 13, 2021 Issued
Array ( [id] => 17630314 [patent_doc_number] => 20220165329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => CONTROLLER AND MEMORY SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/340922 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340922
Controller and memory system for refreshing memory based on fail bits and temperature Jun 6, 2021 Issued
Array ( [id] => 17070416 [patent_doc_number] => 20210272633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MEMORY CELL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/321604 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/321604
Memory cell programming applying a programming pulse having different voltage levels May 16, 2021 Issued
Array ( [id] => 18403718 [patent_doc_number] => 11665878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => CFET SRAM bit cell with two stacked device decks [patent_app_type] => utility [patent_app_number] => 17/316085 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 53 [patent_no_of_words] => 7811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316085
CFET SRAM bit cell with two stacked device decks May 9, 2021 Issued
Array ( [id] => 17599055 [patent_doc_number] => 20220148629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => MEMORY DEVICE, STORAGE DEVICE, AND METHOD OF OPERATING MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/307362 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307362 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/307362
Memory device, storage device, and method of operating memory controller to output read data in response to read enable signal May 3, 2021 Issued
Array ( [id] => 17025218 [patent_doc_number] => 20210249090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THEREOF [patent_app_type] => utility [patent_app_number] => 17/242712 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242712 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242712
Nonvolatile memory device and method for operating with varying programming time Apr 27, 2021 Issued
Array ( [id] => 17908429 [patent_doc_number] => 11462289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Wordline capacitance balancing [patent_app_type] => utility [patent_app_number] => 17/236729 [patent_app_country] => US [patent_app_date] => 2021-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 15775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/236729
Wordline capacitance balancing Apr 20, 2021 Issued
Array ( [id] => 17949008 [patent_doc_number] => 20220336027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => NON-VOLATILE MEMORY DEVICE WITH COMPARISON CAPABILITY BETWEEN TARGET AND READOUT DATA [patent_app_type] => utility [patent_app_number] => 17/234794 [patent_app_country] => US [patent_app_date] => 2021-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234794 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234794
Non-volatile memory device with comparison capability between target and readout data Apr 19, 2021 Issued
Array ( [id] => 17188549 [patent_doc_number] => 20210335434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => OPERATION METHOD OF NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/232370 [patent_app_country] => US [patent_app_date] => 2021-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17232370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/232370
Operation method of nonvolatile memory device Apr 15, 2021 Issued
Array ( [id] => 18507359 [patent_doc_number] => 11705183 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Word line booster circuit and method [patent_app_type] => utility [patent_app_number] => 17/223548 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223548
Word line booster circuit and method Apr 5, 2021 Issued
Array ( [id] => 17025195 [patent_doc_number] => 20210249067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR LATCH RESET LOGIC [patent_app_type] => utility [patent_app_number] => 17/301479 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301479
Apparatuses, systems, and methods for latch reset logic Apr 4, 2021 Issued
Array ( [id] => 17917201 [patent_doc_number] => 20220319597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => KEY STORAGE FOR SORTED STRING TABLES USING CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/301306 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301306
Key storage for sorted string tables using content addressable memory Mar 30, 2021 Issued
Array ( [id] => 16965976 [patent_doc_number] => 20210217475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => MEMORY DEVICES FOR PATTERN MATCHING [patent_app_type] => utility [patent_app_number] => 17/218243 [patent_app_country] => US [patent_app_date] => 2021-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17218243 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/218243
Memory devices for pattern matching Mar 30, 2021 Issued
Array ( [id] => 18276886 [patent_doc_number] => 11615832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Electronic devices executing a refresh operation based on temperature [patent_app_type] => utility [patent_app_number] => 17/210009 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13325 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210009 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210009
Electronic devices executing a refresh operation based on temperature Mar 22, 2021 Issued
Array ( [id] => 17622954 [patent_doc_number] => 11342013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Memory system and operating method to set target command delay time to merge and process read commands [patent_app_type] => utility [patent_app_number] => 17/209956 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10337 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209956
Memory system and operating method to set target command delay time to merge and process read commands Mar 22, 2021 Issued
Array ( [id] => 18073536 [patent_doc_number] => 11532373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Managing error-handling flows in memory devices [patent_app_type] => utility [patent_app_number] => 17/205091 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205091 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205091
Managing error-handling flows in memory devices Mar 17, 2021 Issued
Array ( [id] => 17652470 [patent_doc_number] => 11355206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => High-voltage shifter with degradation compensation [patent_app_type] => utility [patent_app_number] => 17/200317 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/200317
High-voltage shifter with degradation compensation Mar 11, 2021 Issued
Array ( [id] => 17485669 [patent_doc_number] => 20220093173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MEMORY SYSTEM AND POWER SUPPLY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/199830 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7370 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199830 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199830
Memory system and power supply circuit with power loss protection capability Mar 11, 2021 Issued
Array ( [id] => 17630298 [patent_doc_number] => 20220165313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => ELECTRONIC DEVICE FOR PERFORMING DATA BUS INVERSION OPERATION [patent_app_type] => utility [patent_app_number] => 17/197835 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197835 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197835
ELECTRONIC DEVICE FOR PERFORMING DATA BUS INVERSION OPERATION Mar 9, 2021 Abandoned
Array ( [id] => 18623589 [patent_doc_number] => 11756643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Apparatus and method for correcting an error in data transmission of a data processing system [patent_app_type] => utility [patent_app_number] => 17/196578 [patent_app_country] => US [patent_app_date] => 2021-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 17053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17196578 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/196578
Apparatus and method for correcting an error in data transmission of a data processing system Mar 8, 2021 Issued
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