| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 18130043
[patent_doc_number] => 11556250
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs
[patent_app_type] => utility
[patent_app_number] => 16/939814
[patent_app_country] => US
[patent_app_date] => 2020-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7107
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939814
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/939814 | Method and apparatus for temperature-gradient aware data-placement for 3D stacked DRAMs | Jul 26, 2020 | Issued |
Array
(
[id] => 17422975
[patent_doc_number] => 11256429
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-22
[patent_title] => Adjustment of a pre-read operation based on an operating temperature
[patent_app_type] => utility
[patent_app_number] => 16/933577
[patent_app_country] => US
[patent_app_date] => 2020-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7281
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16933577
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/933577 | Adjustment of a pre-read operation based on an operating temperature | Jul 19, 2020 | Issued |
Array
(
[id] => 17173822
[patent_doc_number] => 20210327493
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => DEVICES FOR PERFORMING A REFRESH OPERATION BASED ON POWER CONTROL OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/931192
[patent_app_country] => US
[patent_app_date] => 2020-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12666
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931192
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/931192 | Devices for performing a refresh operation based on power control operation | Jul 15, 2020 | Issued |
Array
(
[id] => 16583972
[patent_doc_number] => 20210018374
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-21
[patent_title] => REMOTE SENSING
[patent_app_type] => utility
[patent_app_number] => 16/919966
[patent_app_country] => US
[patent_app_date] => 2020-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7410
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919966
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/919966 | Apparatus, system and method for remote sensing and resetting electrical characteristics of a memristor | Jul 1, 2020 | Issued |
Array
(
[id] => 17900486
[patent_doc_number] => 20220310148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => SEMICONDUCTOR DEVICE AND WIRELESS COMMUNICATION DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/615867
[patent_app_country] => US
[patent_app_date] => 2020-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 28853
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17615867
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/615867 | Semiconductor device and wireless communication device | Jun 29, 2020 | Issued |
Array
(
[id] => 16364304
[patent_doc_number] => 20200321055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-08
[patent_title] => PRE-CHARGE VOLTAGE FOR INHIBITING UNSELECTED NAND MEMORY CELL PROGRAMMING
[patent_app_type] => utility
[patent_app_number] => 16/907639
[patent_app_country] => US
[patent_app_date] => 2020-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18986
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16907639
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/907639 | Pre-charge voltage for inhibiting unselected NAND memory cell programming | Jun 21, 2020 | Issued |
Array
(
[id] => 17270138
[patent_doc_number] => 11195566
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-07
[patent_title] => Memory device and method for supporting command bus training mode based on one data signal
[patent_app_type] => utility
[patent_app_number] => 16/946217
[patent_app_country] => US
[patent_app_date] => 2020-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 8991
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16946217
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/946217 | Memory device and method for supporting command bus training mode based on one data signal | Jun 9, 2020 | Issued |
Array
(
[id] => 18291634
[patent_doc_number] => 11620505
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-04
[patent_title] => Neuromorphic package devices and neuromorphic computing systems
[patent_app_type] => utility
[patent_app_number] => 16/881963
[patent_app_country] => US
[patent_app_date] => 2020-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 25
[patent_no_of_words] => 11517
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16881963
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/881963 | Neuromorphic package devices and neuromorphic computing systems | May 21, 2020 | Issued |
Array
(
[id] => 17493248
[patent_doc_number] => 11282558
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Ferroelectric random-access memory with ROMFUSE area having redundant configuration wordlines
[patent_app_type] => utility
[patent_app_number] => 16/880902
[patent_app_country] => US
[patent_app_date] => 2020-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6109
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880902
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/880902 | Ferroelectric random-access memory with ROMFUSE area having redundant configuration wordlines | May 20, 2020 | Issued |
Array
(
[id] => 16272019
[patent_doc_number] => 20200273507
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => READ MARGIN CONTROL CIRCUIT DETERMINING DATA VALID WINDOW, MEMORY CONTROLLER INCLUDING THE SAME, AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/871096
[patent_app_country] => US
[patent_app_date] => 2020-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10711
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871096
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/871096 | Memory controller and operating method with read margin control circuit determining data valid window | May 10, 2020 | Issued |
Array
(
[id] => 17455912
[patent_doc_number] => 11270778
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-08
[patent_title] => Method and system for reducing program disturb degradation in flash memory
[patent_app_type] => utility
[patent_app_number] => 16/852162
[patent_app_country] => US
[patent_app_date] => 2020-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 11728
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852162
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/852162 | Method and system for reducing program disturb degradation in flash memory | Apr 16, 2020 | Issued |
Array
(
[id] => 17645027
[patent_doc_number] => 20220172766
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => SEMICONDUCTOR DEVICE AND OPERATION METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/602431
[patent_app_country] => US
[patent_app_date] => 2020-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 50370
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17602431
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/602431 | Semiconductor device including sense amplifier and operation method of semiconductor device | Apr 14, 2020 | Issued |
Array
(
[id] => 17032558
[patent_doc_number] => 11094375
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-17
[patent_title] => Concurrent read and reconfigured write operations in a memory device
[patent_app_type] => utility
[patent_app_number] => 16/807320
[patent_app_country] => US
[patent_app_date] => 2020-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 13402
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807320
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/807320 | Concurrent read and reconfigured write operations in a memory device | Mar 2, 2020 | Issued |
Array
(
[id] => 17195881
[patent_doc_number] => 11164646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-02
[patent_title] => Memory device including massbit counter configured to perform off cell counting and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 16/806398
[patent_app_country] => US
[patent_app_date] => 2020-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 37
[patent_no_of_words] => 15454
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806398
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/806398 | Memory device including massbit counter configured to perform off cell counting and method of operating the same | Mar 1, 2020 | Issued |
Array
(
[id] => 17054414
[patent_doc_number] => 20210263848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-26
[patent_title] => MODIFYING SUBSETS OF MEMORY BANK OPERATING PARAMETERS
[patent_app_type] => utility
[patent_app_number] => 16/796860
[patent_app_country] => US
[patent_app_date] => 2020-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20615
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16796860
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/796860 | Modifying subsets of memory bank operating parameters | Feb 19, 2020 | Issued |
Array
(
[id] => 16865597
[patent_doc_number] => 11024348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Memory array with reduced read power requirements and increased capacity
[patent_app_type] => utility
[patent_app_number] => 16/795787
[patent_app_country] => US
[patent_app_date] => 2020-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 34
[patent_no_of_words] => 18119
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16795787
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/795787 | Memory array with reduced read power requirements and increased capacity | Feb 19, 2020 | Issued |
Array
(
[id] => 17772184
[patent_doc_number] => 11404135
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-02
[patent_title] => Runtime identification of bad memory cells based on difference between data pattern and read data
[patent_app_type] => utility
[patent_app_number] => 16/792770
[patent_app_country] => US
[patent_app_date] => 2020-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6057
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16792770
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/792770 | Runtime identification of bad memory cells based on difference between data pattern and read data | Feb 16, 2020 | Issued |
Array
(
[id] => 17040400
[patent_doc_number] => 20210257036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => DEVICE, SYSTEM, AND METHOD TO VERIFY DATA PROGRAMMING OF A MULTI-LEVEL CELL MEMORY BASED ON ONE OF TEMPERATURE, PRESSURE, WEAR CONDITION OR RELATIVE POSITION OF THE MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 16/790074
[patent_app_country] => US
[patent_app_date] => 2020-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18502
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16790074
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/790074 | Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell | Feb 12, 2020 | Issued |
Array
(
[id] => 16560097
[patent_doc_number] => 20210005246
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-07
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/780377
[patent_app_country] => US
[patent_app_date] => 2020-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10065
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780377
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/780377 | Semiconductor memory device and method for refreshing memory with refresh counter | Feb 2, 2020 | Issued |
Array
(
[id] => 17107231
[patent_doc_number] => 11127456
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-21
[patent_title] => Nonvolatile memory device and method of programing with capability of detecting sudden power off
[patent_app_type] => utility
[patent_app_number] => 16/746413
[patent_app_country] => US
[patent_app_date] => 2020-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9382
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746413
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/746413 | Nonvolatile memory device and method of programing with capability of detecting sudden power off | Jan 16, 2020 | Issued |