Search

Sultana Begum

Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
635
Issued Applications
547
Pending Applications
72
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15905483 [patent_doc_number] => 20200152262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => WEIGHT STORAGE USING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/733152 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/733152
Techniques for programming neural memory unit using cell conditioning Jan 1, 2020 Issued
Array ( [id] => 16423689 [patent_doc_number] => 20200348887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING TEMPERATURE THEREOF [patent_app_type] => utility [patent_app_number] => 16/722856 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722856 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722856
Memory system and method of controlling operations on bad memory block based on temperature Dec 19, 2019 Issued
Array ( [id] => 16904544 [patent_doc_number] => 20210183460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => ROW ADDRESS COMPARATOR FOR A ROW REDUNDANCY CONTROL CIRCUIT IN A MEMORY [patent_app_type] => utility [patent_app_number] => 16/711929 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711929 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/711929
Row address comparator for a row redundancy control circuit in a memory Dec 11, 2019 Issued
Array ( [id] => 18203315 [patent_doc_number] => 11585703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => On-chip temperature sensing with non-volatile memory elements [patent_app_type] => utility [patent_app_number] => 16/700358 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4680 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700358 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700358
On-chip temperature sensing with non-volatile memory elements Dec 1, 2019 Issued
Array ( [id] => 17332216 [patent_doc_number] => 11222684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Refresh control device and memory device for latching an address randomly [patent_app_type] => utility [patent_app_number] => 16/696864 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7350 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696864
Refresh control device and memory device for latching an address randomly Nov 25, 2019 Issued
Array ( [id] => 17288908 [patent_doc_number] => 11205465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Decode circuitry coupled to a memory array [patent_app_type] => utility [patent_app_number] => 16/694133 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5731 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694133
Decode circuitry coupled to a memory array Nov 24, 2019 Issued
Array ( [id] => 17002381 [patent_doc_number] => 11081203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Leakage source detection by scanning access lines [patent_app_type] => utility [patent_app_number] => 16/684533 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10733 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684533
Leakage source detection by scanning access lines Nov 13, 2019 Issued
Array ( [id] => 17253839 [patent_doc_number] => 11189335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Double write/read throughput by CMOS adjacent array (CaA) NAND memory [patent_app_type] => utility [patent_app_number] => 16/683209 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 5044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683209 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683209
Double write/read throughput by CMOS adjacent array (CaA) NAND memory Nov 12, 2019 Issued
Array ( [id] => 17295765 [patent_doc_number] => 20210391604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => SEMICONDUCTOR DEVICE AND SECONDARY BATTERY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/291021 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17291021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/291021
Semiconductor device sensor unit Nov 12, 2019 Issued
Array ( [id] => 16759563 [patent_doc_number] => 10978118 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => DDR SDRAM signal calibration device and method [patent_app_type] => utility [patent_app_number] => 16/682689 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16682689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/682689
DDR SDRAM signal calibration device and method Nov 12, 2019 Issued
Array ( [id] => 16987001 [patent_doc_number] => 11074174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Method for managing flash memory module and associated flash memory controller and electronic device based on timing of dummy read operations [patent_app_type] => utility [patent_app_number] => 16/683191 [patent_app_country] => US [patent_app_date] => 2019-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3833 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683191 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683191
Method for managing flash memory module and associated flash memory controller and electronic device based on timing of dummy read operations Nov 12, 2019 Issued
Array ( [id] => 17091720 [patent_doc_number] => 11119910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments [patent_app_type] => utility [patent_app_number] => 16/598634 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 49 [patent_no_of_words] => 61325 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598634 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598634
Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments Oct 9, 2019 Issued
Array ( [id] => 16765282 [patent_doc_number] => 20210110864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => METHODS OF ACTIVATING INPUT/OUTPUT LINES OF MEMORY DEVICES, AND RELATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/598938 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598938 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598938
Methods of activating input/output lines of memory devices, and related devices and systems Oct 9, 2019 Issued
Array ( [id] => 16788032 [patent_doc_number] => 10990465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => MRAM noise mitigation for background operations by delaying verify timing [patent_app_type] => utility [patent_app_number] => 16/598611 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 49 [patent_no_of_words] => 61322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598611 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598611
MRAM noise mitigation for background operations by delaying verify timing Oct 9, 2019 Issued
Array ( [id] => 16927149 [patent_doc_number] => 11048633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow [patent_app_type] => utility [patent_app_number] => 16/598854 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 49 [patent_no_of_words] => 61322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598854 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598854
Determining an inactive memory bank during an idle memory cycle to prevent error cache overflow Oct 9, 2019 Issued
Array ( [id] => 16788973 [patent_doc_number] => 10991410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Bi-polar write scheme [patent_app_type] => utility [patent_app_number] => 16/598568 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 49 [patent_no_of_words] => 61322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598568
Bi-polar write scheme Oct 9, 2019 Issued
Array ( [id] => 16834042 [patent_doc_number] => 11010294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => MRAM noise mitigation for write operations with simultaneous background operations [patent_app_type] => utility [patent_app_number] => 16/598599 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 49 [patent_no_of_words] => 61323 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598599 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598599
MRAM noise mitigation for write operations with simultaneous background operations Oct 9, 2019 Issued
Array ( [id] => 15773185 [patent_doc_number] => 20200117610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => ERROR CACHE SYSTEM WITH COARSE AND FINE SEGMENTS FOR POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 16/598647 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 61340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598647 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598647
Error cache system with coarse and fine segments for power optimization Oct 9, 2019 Issued
Array ( [id] => 15459251 [patent_doc_number] => 20200042450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => ERROR CACHE SEGMENTATION FOR POWER REDUCTION [patent_app_type] => utility [patent_app_number] => 16/598596 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 61343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598596 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598596
Error cache segmentation for power reduction Oct 9, 2019 Issued
Array ( [id] => 16834950 [patent_doc_number] => 11011208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Semiconductor memory device including parallel substrates in three dimensional structures [patent_app_type] => utility [patent_app_number] => 16/591061 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12110 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591061
Semiconductor memory device including parallel substrates in three dimensional structures Oct 1, 2019 Issued
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