
Sultana Begum
Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 635 |
| Issued Applications | 547 |
| Pending Applications | 72 |
| Abandoned Applications | 34 |
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|---|---|---|---|
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