Search

Sultana Begum

Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
635
Issued Applications
547
Pending Applications
72
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16788977 [patent_doc_number] => 10991414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Granular refresh rate control for memory devices based on bit position [patent_app_type] => utility [patent_app_number] => 16/586903 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17591 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586903 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586903
Granular refresh rate control for memory devices based on bit position Sep 26, 2019 Issued
Array ( [id] => 16668688 [patent_doc_number] => 10937947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Magnetic memory device with a nonmagnet between two ferromagnets of a magnetoresistive effect element [patent_app_type] => utility [patent_app_number] => 16/564123 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9800 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564123
Magnetic memory device with a nonmagnet between two ferromagnets of a magnetoresistive effect element Sep 8, 2019 Issued
Array ( [id] => 17394590 [patent_doc_number] => 11243602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Low power state implementation in a power management circuit [patent_app_type] => utility [patent_app_number] => 16/554896 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5988 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554896
Low power state implementation in a power management circuit Aug 28, 2019 Issued
Array ( [id] => 16495492 [patent_doc_number] => 10861539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Neural network memory [patent_app_type] => utility [patent_app_number] => 16/546520 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11794 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546520 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546520
Neural network memory Aug 20, 2019 Issued
Array ( [id] => 16386267 [patent_doc_number] => 10811108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-20 [patent_title] => Semiconductor memory device and memory system [patent_app_type] => utility [patent_app_number] => 16/537023 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8297 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537023 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537023
Semiconductor memory device and memory system Aug 8, 2019 Issued
Array ( [id] => 17590485 [patent_doc_number] => 11328760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Semiconductor device having interconnection in package and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/527415 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 11668 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527415
Semiconductor device having interconnection in package and method for manufacturing the same Jul 30, 2019 Issued
Array ( [id] => 16928071 [patent_doc_number] => 11049560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Pulsed integrator and memory techniques for determining a state of a memory cell [patent_app_type] => utility [patent_app_number] => 16/518852 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 18235 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518852 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518852
Pulsed integrator and memory techniques for determining a state of a memory cell Jul 21, 2019 Issued
Array ( [id] => 16803123 [patent_doc_number] => 10998074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Wordline capacitance balancing [patent_app_type] => utility [patent_app_number] => 16/518824 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 15727 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518824 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518824
Wordline capacitance balancing Jul 21, 2019 Issued
Array ( [id] => 15122967 [patent_doc_number] => 20190348117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHODS AND APPARATUS FOR PATTERN MATCHING [patent_app_type] => utility [patent_app_number] => 16/517846 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517846
Methods and apparatus for pattern matching in a memory containing sets of memory elements Jul 21, 2019 Issued
Array ( [id] => 15092603 [patent_doc_number] => 20190341113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => MEMORY CELL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 16/516791 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516791 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/516791
Memory cell programming with a program pulse having a plurality of different voltage levels Jul 18, 2019 Issued
Array ( [id] => 16180160 [patent_doc_number] => 20200227129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/514622 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514622 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514622
Semiconductor devices and semiconductor systems that operate with strobe signal during test mode Jul 16, 2019 Issued
Array ( [id] => 16980406 [patent_doc_number] => 20210224643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => MAX POOLING PROCESSOR BASED ON 1T1R MEMORY [patent_app_type] => utility [patent_app_number] => 16/631840 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4641 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16631840 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/631840
Max pooling processor based on 1T1R memory Jul 11, 2019 Issued
Array ( [id] => 17605800 [patent_doc_number] => 11334288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => MRAM access coordination systems and methods with a plurality of pipelines [patent_app_type] => utility [patent_app_number] => 16/442345 [patent_app_country] => US [patent_app_date] => 2019-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9021 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16442345 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/442345
MRAM access coordination systems and methods with a plurality of pipelines Jun 13, 2019 Issued
Array ( [id] => 17010661 [patent_doc_number] => 20210241822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => MEMORY DEVICE HAVING NON-UNIFORM REFRESH [patent_app_type] => utility [patent_app_number] => 16/973241 [patent_app_country] => US [patent_app_date] => 2019-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16973241 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/973241
Memory device having non-uniform refresh May 24, 2019 Issued
Array ( [id] => 16447995 [patent_doc_number] => 10839926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Semiconductor memory device with improved threshold voltage distribution of transistor [patent_app_type] => utility [patent_app_number] => 16/418662 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7967 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418662 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/418662
Semiconductor memory device with improved threshold voltage distribution of transistor May 20, 2019 Issued
Array ( [id] => 16000363 [patent_doc_number] => 20200176052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => DYNAMIC SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 16/418201 [patent_app_country] => US [patent_app_date] => 2019-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16418201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/418201
Dynamic semiconductor memory device and memory system with temperature sensor May 20, 2019 Issued
Array ( [id] => 16454623 [patent_doc_number] => 20200364049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => METHOD AND APPARATUS IN MEMORY FOR INPUT AND OUTPUT PARAMETERS OPTIMIZATION IN A MEMORY SYSTEM DURING OPERATION [patent_app_type] => utility [patent_app_number] => 16/415742 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/415742
Method and apparatus in memory for input and output parameters optimization in a memory system during operation May 16, 2019 Issued
Array ( [id] => 17438756 [patent_doc_number] => 11264096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits [patent_app_type] => utility [patent_app_number] => 16/411573 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11140 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411573
Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits May 13, 2019 Issued
Array ( [id] => 17438756 [patent_doc_number] => 11264096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits [patent_app_type] => utility [patent_app_number] => 16/411573 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11140 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411573
Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits May 13, 2019 Issued
Array ( [id] => 17438756 [patent_doc_number] => 11264096 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits [patent_app_type] => utility [patent_app_number] => 16/411573 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11140 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411573 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411573
Apparatuses, systems, and methods for a content addressable memory cell with latch and comparator circuits May 13, 2019 Issued
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