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Sultana Begum

Examiner (ID: 1295, Phone: (571)431-0691 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
605
Issued Applications
526
Pending Applications
74
Abandoned Applications
33

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19285340 [patent_doc_number] => 20240221817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => WRITE DATA SIGNAL DELAY CONTROL METHOD AND APPARATUS, DEVICE, AND MEDIUM [patent_app_type] => utility [patent_app_number] => 18/604366 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604366 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604366
WRITE DATA SIGNAL DELAY CONTROL METHOD AND APPARATUS, DEVICE, AND MEDIUM Mar 12, 2024 Pending
Array ( [id] => 19467664 [patent_doc_number] => 20240321334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => STORAGE DEVICE AND DRIVING METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/595065 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595065 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/595065
STORAGE DEVICE AND DRIVING METHOD OF STORAGE DEVICE Mar 3, 2024 Pending
Array ( [id] => 20209407 [patent_doc_number] => 20250279127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => LOW ERROR RATE READ OPERATION IN MULTI-MODULE ARRAYS [patent_app_type] => utility [patent_app_number] => 18/591904 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591904
LOW ERROR RATE READ OPERATION IN MULTI-MODULE ARRAYS Feb 28, 2024 Pending
Array ( [id] => 19467666 [patent_doc_number] => 20240321336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => APPARATUS OPERATING IN GEARDOWN MODE [patent_app_type] => utility [patent_app_number] => 18/583267 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583267
Apparatus operating in geardown mode Feb 20, 2024 Issued
Array ( [id] => 19986776 [patent_doc_number] => 20250124998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SEMICONDUCTOR DEVICE FOR CONTROLLING OPERATING POWER SUPPLIED TO WORD LINE DRIVER [patent_app_type] => utility [patent_app_number] => 18/442833 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442833 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442833
SEMICONDUCTOR DEVICE FOR CONTROLLING OPERATING POWER SUPPLIED TO WORD LINE DRIVER Feb 14, 2024 Pending
Array ( [id] => 20167612 [patent_doc_number] => 20250259659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => POWER GATING CIRCUIT WITH MEMORY PRECHARGE SUPPORT [patent_app_type] => utility [patent_app_number] => 18/436422 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436422
POWER GATING CIRCUIT WITH MEMORY PRECHARGE SUPPORT Feb 7, 2024 Pending
Array ( [id] => 19204646 [patent_doc_number] => 20240176545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => FUSE LATCH OF SEMICONDUCTOR DEVICE FOR LATCHING DATA OF A REPAIR FUSE CELL [patent_app_type] => utility [patent_app_number] => 18/432663 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432663 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432663
Fuse latch of semiconductor device for latching data of a repair fuse cell Feb 4, 2024 Issued
Array ( [id] => 20139173 [patent_doc_number] => 20250246217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => MEMORY SYSTEM AND MEMORY DIE [patent_app_type] => utility [patent_app_number] => 18/426356 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426356 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426356
MEMORY SYSTEM AND MEMORY DIE Jan 29, 2024 Pending
Array ( [id] => 19634315 [patent_doc_number] => 20240412764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/419959 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419959 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/419959
RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE Jan 22, 2024 Issued
Array ( [id] => 20088571 [patent_doc_number] => 20250218507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR DATA CALCULATION WITH THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/415252 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415252
MEMORY DEVICE, MEMORY SYSTEM, AND METHOD FOR DATA CALCULATION WITH THE MEMORY DEVICE Jan 16, 2024 Pending
Array ( [id] => 20096102 [patent_doc_number] => 20250226038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => COMPACT SENSE AMPLIFIER DATA LATCH DESIGN WITH VERY LOW VOLTAGE TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/409292 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409292 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409292
COMPACT SENSE AMPLIFIER DATA LATCH DESIGN WITH VERY LOW VOLTAGE TRANSISTORS Jan 9, 2024 Pending
Array ( [id] => 19515417 [patent_doc_number] => 20240347103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/408608 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408608
SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF Jan 9, 2024 Pending
Array ( [id] => 19664342 [patent_doc_number] => 12178047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Semiconductor storage device and method of manufacturing semiconductor storage device [patent_app_type] => utility [patent_app_number] => 18/403916 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 10749 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403916
Semiconductor storage device and method of manufacturing semiconductor storage device Jan 3, 2024 Issued
Array ( [id] => 19130655 [patent_doc_number] => 20240136008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => METHOD AND MEMORY DEVICE WITH INCREASED READ AND WRITE MARGIN [patent_app_type] => utility [patent_app_number] => 18/402647 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402647
Method and memory device with increased read and write margin Jan 1, 2024 Issued
Array ( [id] => 19237049 [patent_doc_number] => 20240194244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => APPARATUSES AND METHODS FOR A MULTI-BIT DUTY CYCLE MONITOR [patent_app_type] => utility [patent_app_number] => 18/397984 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397984
APPARATUSES AND METHODS FOR A MULTI-BIT DUTY CYCLE MONITOR Dec 26, 2023 Pending
Array ( [id] => 19858040 [patent_doc_number] => 12260890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Memory device which generates improved write voltage according to size of memory cell [patent_app_type] => utility [patent_app_number] => 18/545626 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11951 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545626 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545626
Memory device which generates improved write voltage according to size of memory cell Dec 18, 2023 Issued
Array ( [id] => 20036074 [patent_doc_number] => 20250174296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICES, OPERATING METHODS THEREOF, MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/543552 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543552
MEMORY DEVICES, OPERATING METHODS THEREOF, MEMORY SYSTEMS Dec 17, 2023 Pending
Array ( [id] => 19500129 [patent_doc_number] => 20240339147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/527367 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527367
MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF Dec 3, 2023 Pending
Array ( [id] => 19269032 [patent_doc_number] => 20240212736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => WORD LINE CHARGE INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/528451 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528451 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528451
WORD LINE CHARGE INTEGRATION Dec 3, 2023 Pending
Array ( [id] => 20482637 [patent_doc_number] => 12531113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Single-loop memory device, double-loop memory device, and ZQ calibration method [patent_app_type] => utility [patent_app_number] => 18/524136 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3844 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524136
Single-loop memory device, double-loop memory device, and ZQ calibration method Nov 29, 2023 Issued
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