Search

Sultana Begum

Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
635
Issued Applications
547
Pending Applications
72
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20624764 [patent_doc_number] => 12592276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Semiconductor memory device with sense amplifier that operates for two different voltage range and writing method thereof [patent_app_type] => utility [patent_app_number] => 18/408608 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408608
Semiconductor memory device with sense amplifier that operates for two different voltage range and writing method thereof Jan 9, 2024 Issued
Array ( [id] => 19664342 [patent_doc_number] => 12178047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Semiconductor storage device and method of manufacturing semiconductor storage device [patent_app_type] => utility [patent_app_number] => 18/403916 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 10749 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403916
Semiconductor storage device and method of manufacturing semiconductor storage device Jan 3, 2024 Issued
Array ( [id] => 19130655 [patent_doc_number] => 20240136008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => METHOD AND MEMORY DEVICE WITH INCREASED READ AND WRITE MARGIN [patent_app_type] => utility [patent_app_number] => 18/402647 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402647
Method and memory device with increased read and write margin Jan 1, 2024 Issued
Array ( [id] => 19237049 [patent_doc_number] => 20240194244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => APPARATUSES AND METHODS FOR A MULTI-BIT DUTY CYCLE MONITOR [patent_app_type] => utility [patent_app_number] => 18/397984 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397984
Apparatuses and methods for a multi-bit duty cycle monitor Dec 26, 2023 Issued
Array ( [id] => 19858040 [patent_doc_number] => 12260890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Memory device which generates improved write voltage according to size of memory cell [patent_app_type] => utility [patent_app_number] => 18/545626 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11951 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545626 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/545626
Memory device which generates improved write voltage according to size of memory cell Dec 18, 2023 Issued
Array ( [id] => 20915195 [patent_doc_number] => 12712049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Memory devices using defective address information processing circuits, and operating methods, and memory systems thereof [patent_app_type] => utility [patent_app_number] => 18/543552 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10352 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18543552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/543552
MEMORY DEVICES, OPERATING METHODS THEREOF, MEMORY SYSTEMS Dec 17, 2023 Pending
Array ( [id] => 20564838 [patent_doc_number] => 12567452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Word line charge integration [patent_app_type] => utility [patent_app_number] => 18/528451 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528451 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/528451
Word line charge integration Dec 3, 2023 Issued
Array ( [id] => 20977606 [patent_doc_number] => 12738310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-15 [patent_title] => Memory device and method with two refresh cycles [patent_app_type] => utility [patent_app_number] => 18/527367 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6757 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527367
MEMORY DEVICE INCLUDING ROW-HAMMER CELLS AND OPERATING METHOD THEREOF Dec 3, 2023 Pending
Array ( [id] => 20482637 [patent_doc_number] => 12531113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Single-loop memory device, double-loop memory device, and ZQ calibration method [patent_app_type] => utility [patent_app_number] => 18/524136 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3844 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524136
Single-loop memory device, double-loop memory device, and ZQ calibration method Nov 29, 2023 Issued
Array ( [id] => 20266836 [patent_doc_number] => 12437832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Repair techniques for coupled memory dies [patent_app_type] => utility [patent_app_number] => 18/525403 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18525403 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/525403
Repair techniques for coupled memory dies Nov 29, 2023 Issued
Array ( [id] => 20758863 [patent_doc_number] => 12651640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => System error correction code (ECC) circuitry routing [patent_app_type] => utility [patent_app_number] => 18/511440 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511440 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511440
System error correction code (ECC) circuitry routing Nov 15, 2023 Issued
Array ( [id] => 20019316 [patent_doc_number] => 20250157538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => EVEN/ODD WORD LINE DRIVING IN 3D MEMORY [patent_app_type] => utility [patent_app_number] => 18/508554 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508554
Even/odd word line driving in 3D memory Nov 13, 2023 Issued
Array ( [id] => 19022864 [patent_doc_number] => 20240079035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => TEMPERATURE-COMPENSATED TIME ESTIMATE FOR A BLOCK TO REACH A UNIFORM CHARGE LOSS STATE [patent_app_type] => utility [patent_app_number] => 18/509088 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/509088
Temperature-compensated time estimate for a block to reach a uniform charge loss state Nov 13, 2023 Issued
Array ( [id] => 19007407 [patent_doc_number] => 20240071478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/504018 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/504018
SEMICONDUCTOR MEMORY DEVICE Nov 6, 2023 Pending
Array ( [id] => 19687686 [patent_doc_number] => 20250006231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => TRANCEIVER FOR DATA OR SIGNAL TRANSMISSION AND A MEMORY SYSTEM INCLUDING THE TRANCEIVER [patent_app_type] => utility [patent_app_number] => 18/500124 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18500124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/500124
TRANCEIVER FOR DATA OR SIGNAL TRANSMISSION AND A MEMORY SYSTEM INCLUDING THE TRANCEIVER Nov 1, 2023 Pending
Array ( [id] => 18990844 [patent_doc_number] => 20240062813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => DETERMINATION OF A BIAS VOLTAGE TO APPLY TO ONE OR MORE MEMORY CELLS IN A NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/385281 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385281 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/385281
Determination of a bias voltage by applying a series of increasing currents to bit line of memory cell in a neural network Oct 29, 2023 Issued
Array ( [id] => 20581198 [patent_doc_number] => 12573452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Determination of a bias voltage to apply to one or more memory cells [patent_app_type] => utility [patent_app_number] => 18/385256 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 54 [patent_no_of_words] => 11012 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385256 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/385256
Determination of a bias voltage to apply to one or more memory cells Oct 29, 2023 Issued
Array ( [id] => 19850360 [patent_doc_number] => 20250095711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING RESISTOR OFFSET CALIBRATION TRAINING [patent_app_type] => utility [patent_app_number] => 18/384249 [patent_app_country] => US [patent_app_date] => 2023-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384249 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384249
Memory device and memory system for performing resistor offset calibration training Oct 25, 2023 Issued
Array ( [id] => 20214861 [patent_doc_number] => 12411512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Low dropout regulator, clock generating circuit, and memory device [patent_app_type] => utility [patent_app_number] => 18/490240 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490240
Low dropout regulator, clock generating circuit, and memory device Oct 18, 2023 Issued
Array ( [id] => 19348881 [patent_doc_number] => 20240257845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SYSTEM AND METHODS FOR COMMUNICATION OVER MULTIFUNCTION PINS [patent_app_type] => utility [patent_app_number] => 18/381776 [patent_app_country] => US [patent_app_date] => 2023-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18381776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/381776
SYSTEM AND METHODS FOR COMMUNICATION OVER MULTIFUNCTION PINS Oct 18, 2023 Pending
Menu