
Sultana Begum
Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 635 |
| Issued Applications | 547 |
| Pending Applications | 72 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18943765
[patent_doc_number] => 20240038904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => APPARATUSES INCLUDING CAPACITORS INCLUDING MULTIPLE DIELECTRIC MATERIALS
[patent_app_type] => utility
[patent_app_number] => 18/484300
[patent_app_country] => US
[patent_app_date] => 2023-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10518
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484300
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/484300 | APPARATUSES INCLUDING CAPACITORS INCLUDING MULTIPLE DIELECTRIC MATERIALS | Oct 9, 2023 | Pending |
Array
(
[id] => 20746633
[patent_doc_number] => 12646552
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-02
[patent_title] => Memory management method, memory storage device and memory control circuit unit with capability to reduce bit error rate of data
[patent_app_type] => utility
[patent_app_number] => 18/481998
[patent_app_country] => US
[patent_app_date] => 2023-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 6171
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481998
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/481998 | Memory management method, memory storage device and memory control circuit unit with capability to reduce bit error rate of data | Oct 4, 2023 | Issued |
Array
(
[id] => 20159897
[patent_doc_number] => 12386523
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-12
[patent_title] => Techniques for performing write training on a dynamic random-access memory
[patent_app_type] => utility
[patent_app_number] => 18/477421
[patent_app_country] => US
[patent_app_date] => 2023-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8495
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477421
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/477421 | Techniques for performing write training on a dynamic random-access memory | Sep 27, 2023 | Issued |
Array
(
[id] => 20345798
[patent_doc_number] => 12469533
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Calibration apparatus and calibration method of memory device with strong-arm comparator
[patent_app_type] => utility
[patent_app_number] => 18/475246
[patent_app_country] => US
[patent_app_date] => 2023-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475246
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/475246 | Calibration apparatus and calibration method of memory device with strong-arm comparator | Sep 26, 2023 | Issued |
Array
(
[id] => 19865968
[patent_doc_number] => 20250104754
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => CIRCUIT WITH LOGICAL FUNCTION OF COMPUTING-IN-MEMORY, MEMORY DEVICE, AND METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/474214
[patent_app_country] => US
[patent_app_date] => 2023-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4197
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474214
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/474214 | Circuit with logical function of computing-in- memory, memory device, and method thereof | Sep 24, 2023 | Issued |
Array
(
[id] => 19865972
[patent_doc_number] => 20250104758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => Multi Bank Refresh in Volatile Memory Systems
[patent_app_type] => utility
[patent_app_number] => 18/472381
[patent_app_country] => US
[patent_app_date] => 2023-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13529
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472381
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/472381 | Multi Bank Refresh in Volatile Memory Systems | Sep 21, 2023 | Pending |
Array
(
[id] => 19054439
[patent_doc_number] => 20240096408
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => ENHANCED VALLEY TRACKING WITH TRIM SETTING UPDATES IN A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/371308
[patent_app_country] => US
[patent_app_date] => 2023-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9056
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18371308
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/371308 | Enhanced valley tracking with trim setting updates in a memory device | Sep 20, 2023 | Issued |
Array
(
[id] => 19321197
[patent_doc_number] => 20240242743
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/368907
[patent_app_country] => US
[patent_app_date] => 2023-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13405
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368907
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/368907 | Memory device and operating method with temperature compensation circuit | Sep 14, 2023 | Issued |
Array
(
[id] => 19850413
[patent_doc_number] => 20250095764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => CONDUCTANCE MODULATION IN COMPUTATIONAL MEMORY
[patent_app_type] => utility
[patent_app_number] => 18/368158
[patent_app_country] => US
[patent_app_date] => 2023-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10948
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368158
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/368158 | Conductance modulation in computational memory | Sep 13, 2023 | Issued |
Array
(
[id] => 20636576
[patent_doc_number] => 12597457
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Initial setting device of semiconductor memory to determine valid setting
[patent_app_type] => utility
[patent_app_number] => 18/462024
[patent_app_country] => US
[patent_app_date] => 2023-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5597
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462024
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/462024 | Initial setting device of semiconductor memory to determine valid setting | Sep 5, 2023 | Issued |
Array
(
[id] => 18848474
[patent_doc_number] => 20230410878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => AUTOMATED VOLTAGE DEMARCATION (VDM) ADJUSTMENT FOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/242155
[patent_app_country] => US
[patent_app_date] => 2023-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11427
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242155
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/242155 | Automated voltage demarcation (VDM) adjustment for memory device | Sep 4, 2023 | Issued |
Array
(
[id] => 18848500
[patent_doc_number] => 20230410904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => CONTENT ADDRESSABLE MEMORY DEVICE, CONTENT ADDRESSABLE MEMORY CELL AND METHOD FOR SINGLE-BIT MULTI-LEVEL DATA SEARCHING AND COMPARING
[patent_app_type] => utility
[patent_app_number] => 18/459461
[patent_app_country] => US
[patent_app_date] => 2023-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9277
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459461
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/459461 | Content addressable memory device, content addressable memory cell and method for single-bit multi-level data searching and comparing | Aug 31, 2023 | Issued |
Array
(
[id] => 19515408
[patent_doc_number] => 20240347094
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING TARGET REFRESH OPERATION
[patent_app_type] => utility
[patent_app_number] => 18/455631
[patent_app_country] => US
[patent_app_date] => 2023-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6420
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455631
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/455631 | MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING TARGET REFRESH OPERATION | Aug 24, 2023 | Pending |
Array
(
[id] => 18820778
[patent_doc_number] => 20230395119
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => REFRESH ADDRESS COUNTING CIRCUIT AND METHOD, REFRESH ADDRESS READ-WRITE CIRCUIT AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/454104
[patent_app_country] => US
[patent_app_date] => 2023-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6186
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18454104
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/454104 | Refresh address counting circuit and method, refresh address read-write circuit and electronic device | Aug 22, 2023 | Issued |
Array
(
[id] => 20389093
[patent_doc_number] => 12488826
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-02
[patent_title] => Counting control circuit , method for counting control circuit and semiconductor memory with counting control circuit
[patent_app_type] => utility
[patent_app_number] => 18/452518
[patent_app_country] => US
[patent_app_date] => 2023-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 12440
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452518
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/452518 | Counting control circuit , method for counting control circuit and semiconductor memory with counting control circuit | Aug 17, 2023 | Issued |
Array
(
[id] => 19788255
[patent_doc_number] => 20250061934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-20
[patent_title] => MEMORY REFRESH
[patent_app_type] => utility
[patent_app_number] => 18/451988
[patent_app_country] => US
[patent_app_date] => 2023-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7274
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451988
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/451988 | Memory refresh with negative voltage generator | Aug 17, 2023 | Issued |
Array
(
[id] => 20243931
[patent_doc_number] => 12424261
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-23
[patent_title] => Signal sampling circuit with commands/address signal divided into odd and even signals and semiconductor memory
[patent_app_type] => utility
[patent_app_number] => 18/449060
[patent_app_country] => US
[patent_app_date] => 2023-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9358
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 718
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18449060
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/449060 | Signal sampling circuit with commands/address signal divided into odd and even signals and semiconductor memory | Aug 13, 2023 | Issued |
Array
(
[id] => 20258850
[patent_doc_number] => 12431213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-30
[patent_title] => Circuit for calibration control, electronic device and method for calibration control
[patent_app_type] => utility
[patent_app_number] => 18/448340
[patent_app_country] => US
[patent_app_date] => 2023-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5637
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 341
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448340
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/448340 | Circuit for calibration control, electronic device and method for calibration control | Aug 10, 2023 | Issued |
Array
(
[id] => 19957166
[patent_doc_number] => 12327582
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-10
[patent_title] => Memory device and operating method with mechanism to determine victim rows for refreshing
[patent_app_type] => utility
[patent_app_number] => 18/232940
[patent_app_country] => US
[patent_app_date] => 2023-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5022
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232940
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/232940 | Memory device and operating method with mechanism to determine victim rows for refreshing | Aug 10, 2023 | Issued |
Array
(
[id] => 18812191
[patent_doc_number] => 20230386528
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER
[patent_app_type] => utility
[patent_app_number] => 18/232768
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11338
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232768
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/232768 | Circuits and methods for compensating a mismatch in a sense amplifier | Aug 9, 2023 | Issued |