Search

Sultana Begum

Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )

Most Active Art Unit
2824
Art Unit(s)
2824
Total Applications
635
Issued Applications
547
Pending Applications
72
Abandoned Applications
34

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19646259 [patent_doc_number] => 20240420779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => CHANNEL PRE-CHARGE PROCESS FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/230371 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230371 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230371
Channel pre-charge process for memory devices using hole pre-charge operation Aug 3, 2023 Issued
Array ( [id] => 19007484 [patent_doc_number] => 20240071555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY AND MEMORY SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 18/364060 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364060 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364060
Memory with arrays of sense amplifiers and two error checking and correction (ECC) modules Aug 1, 2023 Issued
Array ( [id] => 20080628 [patent_doc_number] => 12354703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Memory device and ZQ calibration method [patent_app_type] => utility [patent_app_number] => 18/364026 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364026 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364026
Memory device and ZQ calibration method Aug 1, 2023 Issued
Array ( [id] => 18789060 [patent_doc_number] => 20230377673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => APPARATUS AND METHOD FOR CORRECTING AN ERROR IN DATA TRANSMISSION OF A DATA PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/362978 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362978 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362978
Apparatus and method for correcting an error in data transmission of a data processing system Jul 31, 2023 Issued
Array ( [id] => 20495161 [patent_doc_number] => 12537037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Integrated circuit with asymmetric arrangements of memory arrays [patent_app_type] => utility [patent_app_number] => 18/361523 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361523
Integrated circuit with asymmetric arrangements of memory arrays Jul 27, 2023 Issued
Array ( [id] => 19007391 [patent_doc_number] => 20240071462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => EFFICIENT PERIODIC BACKEND REFRESH READS FOR REDUCING BIT ERROR RATE IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/227139 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227139
Efficient periodic backend refresh reads for reducing bit error rate in memory devices Jul 26, 2023 Issued
Array ( [id] => 19348914 [patent_doc_number] => 20240257878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => APPARATUS AND METHOD FOR SELECTIVELY REDUCING CHARGE PUMP SPEED DURING ERASE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/355352 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355352 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355352
Apparatus and method for selectively reducing charge pump speed during erase operations Jul 18, 2023 Issued
Array ( [id] => 19539215 [patent_doc_number] => 12131770 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-29 [patent_title] => Word line booster circuit and method [patent_app_type] => utility [patent_app_number] => 18/354399 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354399
Word line booster circuit and method Jul 17, 2023 Issued
Array ( [id] => 20375070 [patent_doc_number] => 12482512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Adaptive refresh rate generator [patent_app_type] => utility [patent_app_number] => 18/343007 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343007
Adaptive refresh rate generator Jun 27, 2023 Issued
Array ( [id] => 20581212 [patent_doc_number] => 12573466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Semiconductor device for detecting defect in word line driver [patent_app_type] => utility [patent_app_number] => 18/341607 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7176 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/341607
Semiconductor device for detecting defect in word line driver Jun 25, 2023 Issued
Array ( [id] => 19499126 [patent_doc_number] => 20240338144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => MASKING SPARSE INPUTS AND OUTPUTS IN NEURAL NETWORK ARRAY [patent_app_type] => utility [patent_app_number] => 18/212066 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212066 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212066
MASKING SPARSE INPUTS AND OUTPUTS IN NEURAL NETWORK ARRAY Jun 19, 2023 Pending
Array ( [id] => 20243932 [patent_doc_number] => 12424262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Voltage supply structure for memory cell capable of securing area margin, semiconductor apparatus including the same, and operating method of the semiconductor apparatus [patent_app_type] => utility [patent_app_number] => 18/334962 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2619 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334962 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334962
Voltage supply structure for memory cell capable of securing area margin, semiconductor apparatus including the same, and operating method of the semiconductor apparatus Jun 13, 2023 Issued
Array ( [id] => 19740984 [patent_doc_number] => 12217823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Memory device for supporting command bus training mode and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/332325 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 9018 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18332325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/332325
Memory device for supporting command bus training mode and method of operating the same Jun 8, 2023 Issued
Array ( [id] => 20922310 [patent_doc_number] => 12717369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Voltage regulators with shared decoupling capacitor for memory devices [patent_app_type] => utility [patent_app_number] => 18/331620 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 4409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331620 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331620
VOLTAGE REGULATORS WITH SHARED DECOUPLING CAPACITOR FOR MEMORY DEVICES Jun 7, 2023 Pending
Array ( [id] => 18789065 [patent_doc_number] => 20230377679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => STACKED INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/331012 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331012 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331012
Stacked integrated circuit Jun 6, 2023 Issued
Array ( [id] => 18661108 [patent_doc_number] => 20230307121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SYSTEM AND METHOD FOR COORDINATED MOTION AMONG HETEROGENEOUS DEVICES [patent_app_type] => utility [patent_app_number] => 18/325698 [patent_app_country] => US [patent_app_date] => 2023-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325698 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325698
System and method for coordinated motion among heterogeneous devices May 29, 2023 Issued
Array ( [id] => 19384297 [patent_doc_number] => 20240274167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/324164 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9364 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324164
Semiconductor device and operating method with page buffer including latches May 25, 2023 Issued
Array ( [id] => 19376441 [patent_doc_number] => 12068019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Internal voltage generation circuit and semiconductor memory apparatus including the same [patent_app_type] => utility [patent_app_number] => 18/322409 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6455 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322409
Internal voltage generation circuit and semiconductor memory apparatus including the same May 22, 2023 Issued
Array ( [id] => 19559635 [patent_doc_number] => 20240371427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Runtime Memory Services in Physical Layer [patent_app_type] => utility [patent_app_number] => 18/310872 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310872 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310872
Runtime memory services in physical layer May 1, 2023 Issued
Array ( [id] => 18677651 [patent_doc_number] => 20230315297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => MEMORY SYSTEM FOR CONTROLLING HETEROGENEOUS CLOCK SIGNAL DELAY MODES, METHOD OF OPERATING THE MEMORY SYSTEM, AND MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/295087 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295087 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295087
Memory system for controlling heterogeneous clock signal delay modes, method of operating the memory system, and memory controller Apr 2, 2023 Issued
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