
Sultana Begum
Examiner (ID: 5477, Phone: (571)431-0691 , Office: P/2824 )
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824 |
| Total Applications | 635 |
| Issued Applications | 547 |
| Pending Applications | 72 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18351281
[patent_doc_number] => 20230139392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-04
[patent_title] => STORAGE DEVICE AND A METHOD OF CONTROLLING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/866765
[patent_app_country] => US
[patent_app_date] => 2022-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866765
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/866765 | Storage device with eye open monitoring (EOM) circuit and method to control | Jul 17, 2022 | Issued |
Array
(
[id] => 18365294
[patent_doc_number] => 20230146885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-11
[patent_title] => NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/863037
[patent_app_country] => US
[patent_app_date] => 2022-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12175
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863037
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/863037 | Nonvolatile memory device and operating method with operational amplifier having feedback path | Jul 11, 2022 | Issued |
Array
(
[id] => 19108464
[patent_doc_number] => 11961577
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-16
[patent_title] => Testing of on-chip analog-mixed signal circuits using on-chip memory
[patent_app_type] => utility
[patent_app_number] => 17/810671
[patent_app_country] => US
[patent_app_date] => 2022-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 8961
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810671
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/810671 | Testing of on-chip analog-mixed signal circuits using on-chip memory | Jul 4, 2022 | Issued |
Array
(
[id] => 19539240
[patent_doc_number] => 12131795
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-29
[patent_title] => Adaptive temperature compensation for a memory device
[patent_app_type] => utility
[patent_app_number] => 17/856691
[patent_app_country] => US
[patent_app_date] => 2022-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8362
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17856691
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/856691 | Adaptive temperature compensation for a memory device | Jun 30, 2022 | Issued |
Array
(
[id] => 18721259
[patent_doc_number] => 11798611
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-24
[patent_title] => Memory access controller with refresher and scrubbing mechanism and memory access control method thereof
[patent_app_type] => utility
[patent_app_number] => 17/853972
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 11500
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853972
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/853972 | Memory access controller with refresher and scrubbing mechanism and memory access control method thereof | Jun 29, 2022 | Issued |
Array
(
[id] => 18820806
[patent_doc_number] => 20230395147
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => FORWARD-LOOKING DETERMINATION OF READ VOLTAGE USING MEMORY CELL PATTERNS
[patent_app_type] => utility
[patent_app_number] => 17/855483
[patent_app_country] => US
[patent_app_date] => 2022-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13677
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855483
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/855483 | FORWARD-LOOKING DETERMINATION OF READ VOLTAGE USING MEMORY CELL PATTERNS | Jun 29, 2022 | Pending |
Array
(
[id] => 19596786
[patent_doc_number] => 12154639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-26
[patent_title] => Memory fault notification
[patent_app_type] => utility
[patent_app_number] => 17/851721
[patent_app_country] => US
[patent_app_date] => 2022-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 12632
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851721
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/851721 | Memory fault notification | Jun 27, 2022 | Issued |
Array
(
[id] => 17932998
[patent_doc_number] => 20220328124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => METHOD AND MEMORY DEVICE WITH INCREASED READ AND WRITE MARGIN
[patent_app_type] => utility
[patent_app_number] => 17/848416
[patent_app_country] => US
[patent_app_date] => 2022-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6533
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848416
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/848416 | Method and memory device with increased read and write margin | Jun 23, 2022 | Issued |
Array
(
[id] => 19610804
[patent_doc_number] => 12159684
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-03
[patent_title] => Memory device with memory pillar inside conductor
[patent_app_type] => utility
[patent_app_number] => 17/807802
[patent_app_country] => US
[patent_app_date] => 2022-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 53
[patent_figures_cnt] => 53
[patent_no_of_words] => 22813
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807802
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/807802 | Memory device with memory pillar inside conductor | Jun 19, 2022 | Issued |
Array
(
[id] => 18721681
[patent_doc_number] => 11799038
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-24
[patent_title] => Apparatuses including capacitors including multiple dielectric materials, and related methods
[patent_app_type] => utility
[patent_app_number] => 17/807831
[patent_app_country] => US
[patent_app_date] => 2022-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 10504
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807831
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/807831 | Apparatuses including capacitors including multiple dielectric materials, and related methods | Jun 19, 2022 | Issued |
Array
(
[id] => 18833543
[patent_doc_number] => 20230402070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => APPARATUSES AND METHODS OF MEMORY ACCESS CONTROL
[patent_app_type] => utility
[patent_app_number] => 17/840461
[patent_app_country] => US
[patent_app_date] => 2022-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5183
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840461
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/840461 | Apparatuses and methods of memory access control with section predecoding and section selection | Jun 13, 2022 | Issued |
Array
(
[id] => 18472677
[patent_doc_number] => 20230206965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => DATA PROCESSING CIRCUIT AND SEMICONDUCTOR MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/806248
[patent_app_country] => US
[patent_app_date] => 2022-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9795
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806248
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/806248 | Data processing circuit and semiconductor memory divided into segments | Jun 8, 2022 | Issued |
Array
(
[id] => 19314197
[patent_doc_number] => 12040021
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-16
[patent_title] => Layout of semiconductor structure comprising column decoder
[patent_app_type] => utility
[patent_app_number] => 17/805517
[patent_app_country] => US
[patent_app_date] => 2022-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5225
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805517
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/805517 | Layout of semiconductor structure comprising column decoder | Jun 5, 2022 | Issued |
Array
(
[id] => 19740982
[patent_doc_number] => 12217821
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Storage device and operating method with multiple channels
[patent_app_type] => utility
[patent_app_number] => 17/831969
[patent_app_country] => US
[patent_app_date] => 2022-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 10619
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831969
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/831969 | Storage device and operating method with multiple channels | Jun 2, 2022 | Issued |
Array
(
[id] => 18088377
[patent_doc_number] => 11538516
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-27
[patent_title] => Column selector architecture with edge mat optimization
[patent_app_type] => utility
[patent_app_number] => 17/832097
[patent_app_country] => US
[patent_app_date] => 2022-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6813
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832097
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/832097 | Column selector architecture with edge mat optimization | Jun 2, 2022 | Issued |
Array
(
[id] => 19507611
[patent_doc_number] => 12119040
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-15
[patent_title] => Memory power control by enable circuit
[patent_app_type] => utility
[patent_app_number] => 17/832186
[patent_app_country] => US
[patent_app_date] => 2022-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6763
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832186
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/832186 | Memory power control by enable circuit | Jun 2, 2022 | Issued |
Array
(
[id] => 19399526
[patent_doc_number] => 12073912
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-27
[patent_title] => Apparatuses and methods for command decoding with series connected latches
[patent_app_type] => utility
[patent_app_number] => 17/752605
[patent_app_country] => US
[patent_app_date] => 2022-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10164
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752605
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/752605 | Apparatuses and methods for command decoding with series connected latches | May 23, 2022 | Issued |
Array
(
[id] => 17839502
[patent_doc_number] => 20220276807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => MRAM ACCESS COORDINATION SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 17/745839
[patent_app_country] => US
[patent_app_date] => 2022-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9044
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745839
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/745839 | MRAM access coordination systems and methods via pipeline in parallel | May 15, 2022 | Issued |
Array
(
[id] => 18721250
[patent_doc_number] => 11798602
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-10-24
[patent_title] => Data receiving circuit with latch and equalizer
[patent_app_type] => utility
[patent_app_number] => 17/741884
[patent_app_country] => US
[patent_app_date] => 2022-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3865
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741884
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/741884 | Data receiving circuit with latch and equalizer | May 10, 2022 | Issued |
Array
(
[id] => 19294330
[patent_doc_number] => 12033691
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Readout circuit layout structure, readout circuit, and memory layout structure
[patent_app_type] => utility
[patent_app_number] => 17/662753
[patent_app_country] => US
[patent_app_date] => 2022-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 9147
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 379
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662753
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/662753 | Readout circuit layout structure, readout circuit, and memory layout structure | May 9, 2022 | Issued |