
Sumati Lefkowitz
Examiner (ID: 3406)
| Most Active Art Unit | 2781 |
| Art Unit(s) | 2781, 2662, 2189, 2112, 2181, 2694, 2672, 2666, 2629, 2305 |
| Total Applications | 516 |
| Issued Applications | 375 |
| Pending Applications | 27 |
| Abandoned Applications | 115 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1471866
[patent_doc_number] => 06460099
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Apparatus for expansion of single channel AT Attachment/IDE interface'
[patent_app_type] => B1
[patent_app_number] => 09/353330
[patent_app_country] => US
[patent_app_date] => 1999-07-14
[patent_effective_date] => 0000-00-00
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/460/06460099.pdf
[firstpage_image] =>[orig_patent_app_number] => 09353330
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353330 | Apparatus for expansion of single channel AT Attachment/IDE interface | Jul 13, 1999 | Issued |
Array
(
[id] => 1601962
[patent_doc_number] => 06385686
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[patent_kind] => B1
[patent_issue_date] => 2002-05-07
[patent_title] => 'Apparatus for supporting multiple delayed read transactions between computer buses'
[patent_app_type] => B1
[patent_app_number] => 09/352720
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[patent_app_date] => 1999-07-13
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Array
(
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[patent_doc_number] => 06381667
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[patent_issue_date] => 2002-04-30
[patent_title] => 'Method for supporting multiple delayed read transactions between computer buses'
[patent_app_type] => B1
[patent_app_number] => 09/352721
[patent_app_country] => US
[patent_app_date] => 1999-07-13
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Array
(
[id] => 1289342
[patent_doc_number] => 06647502
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-11
[patent_title] => 'Method and apparatus for providing power based on the amount of data stored in buffers'
[patent_app_type] => B1
[patent_app_number] => 09/352384
[patent_app_country] => US
[patent_app_date] => 1999-07-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/352384 | Method and apparatus for providing power based on the amount of data stored in buffers | Jul 12, 1999 | Issued |
Array
(
[id] => 1601935
[patent_doc_number] => 06385676
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[patent_issue_date] => 2002-05-07
[patent_title] => 'Coherent ordering queue for computer system'
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[patent_app_number] => 09/351988
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[firstpage_image] =>[orig_patent_app_number] => 09351988
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/351988 | Coherent ordering queue for computer system | Jul 11, 1999 | Issued |
Array
(
[id] => 1480980
[patent_doc_number] => 06389502
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[patent_issue_date] => 2002-05-14
[patent_title] => 'Synchronous communication setting method in bus network, bus network utilizing the method thereof and information provision medium'
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[patent_app_number] => 09/351501
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Array
(
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[patent_title] => 'Method for releasing isochronous transaction in bus network, bus network utilizing the method thereof and information provision medium'
[patent_app_type] => B1
[patent_app_number] => 09/351460
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/351460 | Method for releasing isochronous transaction in bus network, bus network utilizing the method thereof and information provision medium | Jul 11, 1999 | Issued |
Array
(
[id] => 1508964
[patent_doc_number] => 06467006
[patent_country] => US
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[patent_issue_date] => 2002-10-15
[patent_title] => 'Topology-independent priority arbitration for stackable frame switches'
[patent_app_type] => B1
[patent_app_number] => 09/350738
[patent_app_country] => US
[patent_app_date] => 1999-07-09
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[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/467/06467006.pdf
[firstpage_image] =>[orig_patent_app_number] => 09350738
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/350738 | Topology-independent priority arbitration for stackable frame switches | Jul 8, 1999 | Issued |
Array
(
[id] => 1049674
[patent_doc_number] => 06865682
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-08
[patent_title] => 'Microprocessor module with integrated voltage regulators'
[patent_app_type] => utility
[patent_app_number] => 09/335940
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/335940 | Microprocessor module with integrated voltage regulators | Jun 17, 1999 | Issued |
Array
(
[id] => 1572257
[patent_doc_number] => 06378022
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[patent_issue_date] => 2002-04-23
[patent_title] => 'Method and apparatus for processing interruptible, multi-cycle instructions'
[patent_app_type] => B1
[patent_app_number] => 09/335105
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/335105 | Method and apparatus for processing interruptible, multi-cycle instructions | Jun 16, 1999 | Issued |
Array
(
[id] => 1466121
[patent_doc_number] => 06393506
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[patent_title] => 'Virtual channel bus and system architecture'
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[patent_app_number] => 09/334144
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/334144 | Virtual channel bus and system architecture | Jun 14, 1999 | Issued |
Array
(
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Array
(
[id] => 1580265
[patent_doc_number] => 06470410
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Array
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Array
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Array
(
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[patent_title] => 'Flash memory'
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Array
(
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Array
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Array
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Array
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