Search

Sumati Lefkowitz

Examiner (ID: 3406)

Most Active Art Unit
2781
Art Unit(s)
2781, 2662, 2189, 2112, 2181, 2694, 2672, 2666, 2629, 2305
Total Applications
516
Issued Applications
375
Pending Applications
27
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1471866 [patent_doc_number] => 06460099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Apparatus for expansion of single channel AT Attachment/IDE interface' [patent_app_type] => B1 [patent_app_number] => 09/353330 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4838 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460099.pdf [firstpage_image] =>[orig_patent_app_number] => 09353330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353330
Apparatus for expansion of single channel AT Attachment/IDE interface Jul 13, 1999 Issued
Array ( [id] => 1601962 [patent_doc_number] => 06385686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Apparatus for supporting multiple delayed read transactions between computer buses' [patent_app_type] => B1 [patent_app_number] => 09/352720 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2760 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385686.pdf [firstpage_image] =>[orig_patent_app_number] => 09352720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352720
Apparatus for supporting multiple delayed read transactions between computer buses Jul 12, 1999 Issued
Array ( [id] => 7634999 [patent_doc_number] => 06381667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Method for supporting multiple delayed read transactions between computer buses' [patent_app_type] => B1 [patent_app_number] => 09/352721 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381667.pdf [firstpage_image] =>[orig_patent_app_number] => 09352721 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352721
Method for supporting multiple delayed read transactions between computer buses Jul 12, 1999 Issued
Array ( [id] => 1289342 [patent_doc_number] => 06647502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method and apparatus for providing power based on the amount of data stored in buffers' [patent_app_type] => B1 [patent_app_number] => 09/352384 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5249 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647502.pdf [firstpage_image] =>[orig_patent_app_number] => 09352384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352384
Method and apparatus for providing power based on the amount of data stored in buffers Jul 12, 1999 Issued
Array ( [id] => 1601935 [patent_doc_number] => 06385676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Coherent ordering queue for computer system' [patent_app_type] => B1 [patent_app_number] => 09/351988 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385676.pdf [firstpage_image] =>[orig_patent_app_number] => 09351988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351988
Coherent ordering queue for computer system Jul 11, 1999 Issued
Array ( [id] => 1480980 [patent_doc_number] => 06389502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Synchronous communication setting method in bus network, bus network utilizing the method thereof and information provision medium' [patent_app_type] => B1 [patent_app_number] => 09/351501 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 21812 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389502.pdf [firstpage_image] =>[orig_patent_app_number] => 09351501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351501
Synchronous communication setting method in bus network, bus network utilizing the method thereof and information provision medium Jul 11, 1999 Issued
Array ( [id] => 1474877 [patent_doc_number] => 06408355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Method for releasing isochronous transaction in bus network, bus network utilizing the method thereof and information provision medium' [patent_app_type] => B1 [patent_app_number] => 09/351460 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 21845 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408355.pdf [firstpage_image] =>[orig_patent_app_number] => 09351460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351460
Method for releasing isochronous transaction in bus network, bus network utilizing the method thereof and information provision medium Jul 11, 1999 Issued
Array ( [id] => 1508964 [patent_doc_number] => 06467006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Topology-independent priority arbitration for stackable frame switches' [patent_app_type] => B1 [patent_app_number] => 09/350738 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6016 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467006.pdf [firstpage_image] =>[orig_patent_app_number] => 09350738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350738
Topology-independent priority arbitration for stackable frame switches Jul 8, 1999 Issued
Array ( [id] => 1049674 [patent_doc_number] => 06865682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-08 [patent_title] => 'Microprocessor module with integrated voltage regulators' [patent_app_type] => utility [patent_app_number] => 09/335940 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3028 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/865/06865682.pdf [firstpage_image] =>[orig_patent_app_number] => 09335940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335940
Microprocessor module with integrated voltage regulators Jun 17, 1999 Issued
Array ( [id] => 1572257 [patent_doc_number] => 06378022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method and apparatus for processing interruptible, multi-cycle instructions' [patent_app_type] => B1 [patent_app_number] => 09/335105 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6531 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378022.pdf [firstpage_image] =>[orig_patent_app_number] => 09335105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335105
Method and apparatus for processing interruptible, multi-cycle instructions Jun 16, 1999 Issued
Array ( [id] => 1466121 [patent_doc_number] => 06393506 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Virtual channel bus and system architecture' [patent_app_type] => B1 [patent_app_number] => 09/334144 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5820 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393506.pdf [firstpage_image] =>[orig_patent_app_number] => 09334144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334144
Virtual channel bus and system architecture Jun 14, 1999 Issued
Array ( [id] => 1429717 [patent_doc_number] => 06510485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Stabilizing circuit for interfacing device' [patent_app_type] => B1 [patent_app_number] => 09/333263 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5054 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510485.pdf [firstpage_image] =>[orig_patent_app_number] => 09333263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333263
Stabilizing circuit for interfacing device Jun 14, 1999 Issued
Array ( [id] => 1580265 [patent_doc_number] => 06470410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Target side concentrator mechanism for connecting multiple logical pipes to a single function utilizing a computer interconnection bus' [patent_app_type] => B1 [patent_app_number] => 09/330527 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 46 [patent_no_of_words] => 25213 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470410.pdf [firstpage_image] =>[orig_patent_app_number] => 09330527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330527
Target side concentrator mechanism for connecting multiple logical pipes to a single function utilizing a computer interconnection bus Jun 10, 1999 Issued
Array ( [id] => 1456669 [patent_doc_number] => 06457084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Target side distributor mechanism for connecting multiple functions to a single logical pipe of a computer interconnection bus' [patent_app_type] => B1 [patent_app_number] => 09/330528 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 46 [patent_no_of_words] => 25180 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457084.pdf [firstpage_image] =>[orig_patent_app_number] => 09330528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330528
Target side distributor mechanism for connecting multiple functions to a single logical pipe of a computer interconnection bus Jun 10, 1999 Issued
Array ( [id] => 1604517 [patent_doc_number] => 06434703 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Event initiation bus and associated fault protection for a telecommunications device' [patent_app_type] => B1 [patent_app_number] => 09/328173 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434703.pdf [firstpage_image] =>[orig_patent_app_number] => 09328173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/328173
Event initiation bus and associated fault protection for a telecommunications device Jun 7, 1999 Issued
Array ( [id] => 1480970 [patent_doc_number] => 06389500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Flash memory' [patent_app_type] => B1 [patent_app_number] => 09/322736 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2510 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389500.pdf [firstpage_image] =>[orig_patent_app_number] => 09322736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322736
Flash memory May 27, 1999 Issued
Array ( [id] => 1572280 [patent_doc_number] => 06378026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Connection detection circuit and method' [patent_app_type] => B1 [patent_app_number] => 09/317502 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4978 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/378/06378026.pdf [firstpage_image] =>[orig_patent_app_number] => 09317502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317502
Connection detection circuit and method May 23, 1999 Issued
Array ( [id] => 1466646 [patent_doc_number] => 06351783 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method and apparatus for isochronous data transport over an asynchronous bus' [patent_app_type] => B1 [patent_app_number] => 09/315859 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5550 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351783.pdf [firstpage_image] =>[orig_patent_app_number] => 09315859 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315859
Method and apparatus for isochronous data transport over an asynchronous bus May 19, 1999 Issued
Array ( [id] => 7638644 [patent_doc_number] => 06397277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method and apparatus for transmitting data over data bus at maximum speed' [patent_app_type] => B1 [patent_app_number] => 09/315092 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 7496 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397277.pdf [firstpage_image] =>[orig_patent_app_number] => 09315092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315092
Method and apparatus for transmitting data over data bus at maximum speed May 18, 1999 Issued
Array ( [id] => 1567591 [patent_doc_number] => 06438700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'System and method to reduce power consumption in advanced RISC machine (ARM) based systems' [patent_app_type] => B1 [patent_app_number] => 09/313933 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4734 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438700.pdf [firstpage_image] =>[orig_patent_app_number] => 09313933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313933
System and method to reduce power consumption in advanced RISC machine (ARM) based systems May 17, 1999 Issued
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