
Sumati Lefkowitz
Supervisory Patent Examiner (ID: 13987, Phone: (571)272-3638 , Office: P/2666 )
| Most Active Art Unit | 2781 |
| Art Unit(s) | 2694, 2672, 2189, 2662, 2629, 2305, 2781, 2181, 2112, 2666 |
| Total Applications | 519 |
| Issued Applications | 375 |
| Pending Applications | 30 |
| Abandoned Applications | 115 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4254861
[patent_doc_number] => 06119192
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Circuit and method for configuring a bus bridge using parameters from a supplemental parameter memory'
[patent_app_type] => 1
[patent_app_number] => 9/176386
[patent_app_country] => US
[patent_app_date] => 1998-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3841
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119192.pdf
[firstpage_image] =>[orig_patent_app_number] => 176386
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/176386 | Circuit and method for configuring a bus bridge using parameters from a supplemental parameter memory | Oct 20, 1998 | Issued |
Array
(
[id] => 4374353
[patent_doc_number] => 06170021
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Server computer I/O redirection tool'
[patent_app_type] => 1
[patent_app_number] => 9/175802
[patent_app_country] => US
[patent_app_date] => 1998-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4587
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/170/06170021.pdf
[firstpage_image] =>[orig_patent_app_number] => 175802
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/175802 | Server computer I/O redirection tool | Oct 18, 1998 | Issued |
Array
(
[id] => 4177513
[patent_doc_number] => 06108740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-22
[patent_title] => 'Method and apparatus for terminating a bus such that stub length requirements are met'
[patent_app_type] => 1
[patent_app_number] => 9/172563
[patent_app_country] => US
[patent_app_date] => 1998-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7835
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/108/06108740.pdf
[firstpage_image] =>[orig_patent_app_number] => 172563
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/172563 | Method and apparatus for terminating a bus such that stub length requirements are met | Oct 13, 1998 | Issued |
Array
(
[id] => 4115943
[patent_doc_number] => 06067591
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Method and apparatus for avoidance of invalid transactions in a bus host controller'
[patent_app_type] => 1
[patent_app_number] => 9/168374
[patent_app_country] => US
[patent_app_date] => 1998-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4224
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/067/06067591.pdf
[firstpage_image] =>[orig_patent_app_number] => 168374
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/168374 | Method and apparatus for avoidance of invalid transactions in a bus host controller | Oct 7, 1998 | Issued |
Array
(
[id] => 4323721
[patent_doc_number] => 06189065
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Method and apparatus for interrupt load balancing for powerPC processors'
[patent_app_type] => 1
[patent_app_number] => 9/161622
[patent_app_country] => US
[patent_app_date] => 1998-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3320
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/189/06189065.pdf
[firstpage_image] =>[orig_patent_app_number] => 161622
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/161622 | Method and apparatus for interrupt load balancing for powerPC processors | Sep 27, 1998 | Issued |
Array
(
[id] => 4280450
[patent_doc_number] => 06260092
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Point to point or ring connectable bus bridge and an interface with method for enhancing link performance in a point to point connectable bus bridge system using the fiber channel'
[patent_app_type] => 1
[patent_app_number] => 9/159424
[patent_app_country] => US
[patent_app_date] => 1998-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5989
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/260/06260092.pdf
[firstpage_image] =>[orig_patent_app_number] => 159424
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/159424 | Point to point or ring connectable bus bridge and an interface with method for enhancing link performance in a point to point connectable bus bridge system using the fiber channel | Sep 23, 1998 | Issued |
Array
(
[id] => 4381828
[patent_doc_number] => 06256744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Personal computer component signal line isolation for an auxiliary powered component'
[patent_app_type] => 1
[patent_app_number] => 9/158962
[patent_app_country] => US
[patent_app_date] => 1998-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4441
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/256/06256744.pdf
[firstpage_image] =>[orig_patent_app_number] => 158962
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/158962 | Personal computer component signal line isolation for an auxiliary powered component | Sep 20, 1998 | Issued |
Array
(
[id] => 4422536
[patent_doc_number] => 06233690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-15
[patent_title] => 'Mechanism for saving power on long latency stalls'
[patent_app_type] => 1
[patent_app_number] => 9/156552
[patent_app_country] => US
[patent_app_date] => 1998-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4648
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/233/06233690.pdf
[firstpage_image] =>[orig_patent_app_number] => 156552
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/156552 | Mechanism for saving power on long latency stalls | Sep 16, 1998 | Issued |
Array
(
[id] => 4254829
[patent_doc_number] => 06119191
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Performing PCI access cycles through PCI bridge hub routing'
[patent_app_type] => 1
[patent_app_number] => 9/144869
[patent_app_country] => US
[patent_app_date] => 1998-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 1992
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119191.pdf
[firstpage_image] =>[orig_patent_app_number] => 144869
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/144869 | Performing PCI access cycles through PCI bridge hub routing | Aug 31, 1998 | Issued |
Array
(
[id] => 4167091
[patent_doc_number] => 06065088
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'System and method for interrupt command queuing and ordering'
[patent_app_type] => 1
[patent_app_number] => 9/144580
[patent_app_country] => US
[patent_app_date] => 1998-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4994
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/065/06065088.pdf
[firstpage_image] =>[orig_patent_app_number] => 144580
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/144580 | System and method for interrupt command queuing and ordering | Aug 30, 1998 | Issued |
Array
(
[id] => 4317596
[patent_doc_number] => 06185650
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'High performance locking facility'
[patent_app_type] => 1
[patent_app_number] => 9/143328
[patent_app_country] => US
[patent_app_date] => 1998-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4283
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/185/06185650.pdf
[firstpage_image] =>[orig_patent_app_number] => 143328
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143328 | High performance locking facility | Aug 27, 1998 | Issued |
Array
(
[id] => 4325211
[patent_doc_number] => 06253274
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Apparatus for a high performance locking facility'
[patent_app_type] => 1
[patent_app_number] => 9/143632
[patent_app_country] => US
[patent_app_date] => 1998-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 4218
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/253/06253274.pdf
[firstpage_image] =>[orig_patent_app_number] => 143632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/143632 | Apparatus for a high performance locking facility | Aug 27, 1998 | Issued |
Array
(
[id] => 4294388
[patent_doc_number] => 06324602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-27
[patent_title] => 'Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion'
[patent_app_type] => 1
[patent_app_number] => 9/135986
[patent_app_country] => US
[patent_app_date] => 1998-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 9419
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/324/06324602.pdf
[firstpage_image] =>[orig_patent_app_number] => 135986
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/135986 | Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion | Aug 16, 1998 | Issued |
Array
(
[id] => 4298383
[patent_doc_number] => 06282600
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Method and apparatus of resolving conflicting register access requests from a service processor and system processor'
[patent_app_type] => 1
[patent_app_number] => 9/134338
[patent_app_country] => US
[patent_app_date] => 1998-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2468
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/282/06282600.pdf
[firstpage_image] =>[orig_patent_app_number] => 134338
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/134338 | Method and apparatus of resolving conflicting register access requests from a service processor and system processor | Aug 13, 1998 | Issued |
Array
(
[id] => 4379420
[patent_doc_number] => 06192439
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'PCI-compliant interrupt steering architecture'
[patent_app_type] => 1
[patent_app_number] => 9/132620
[patent_app_country] => US
[patent_app_date] => 1998-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4349
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/192/06192439.pdf
[firstpage_image] =>[orig_patent_app_number] => 132620
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/132620 | PCI-compliant interrupt steering architecture | Aug 10, 1998 | Issued |
Array
(
[id] => 4195544
[patent_doc_number] => 06085332
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Reset design for redundant raid controllers'
[patent_app_type] => 1
[patent_app_number] => 9/130965
[patent_app_country] => US
[patent_app_date] => 1998-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4254
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/085/06085332.pdf
[firstpage_image] =>[orig_patent_app_number] => 130965
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/130965 | Reset design for redundant raid controllers | Aug 6, 1998 | Issued |
Array
(
[id] => 4238734
[patent_doc_number] => 06088752
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Method and apparatus for exchanging information between buses in a portable computer and docking station through a bridge employing a serial link'
[patent_app_type] => 1
[patent_app_number] => 9/130057
[patent_app_country] => US
[patent_app_date] => 1998-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 6935
[patent_no_of_claims] => 64
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/088/06088752.pdf
[firstpage_image] =>[orig_patent_app_number] => 130057
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/130057 | Method and apparatus for exchanging information between buses in a portable computer and docking station through a bridge employing a serial link | Aug 5, 1998 | Issued |
Array
(
[id] => 4088497
[patent_doc_number] => 06070214
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'Serially linked bus bridge for expanding access over a first bus to a second bus'
[patent_app_type] => 1
[patent_app_number] => 9/130058
[patent_app_country] => US
[patent_app_date] => 1998-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 7113
[patent_no_of_claims] => 81
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/070/06070214.pdf
[firstpage_image] =>[orig_patent_app_number] => 130058
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/130058 | Serially linked bus bridge for expanding access over a first bus to a second bus | Aug 5, 1998 | Issued |
Array
(
[id] => 4312693
[patent_doc_number] => 06237101
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Microprocessor including controller for reduced power consumption and method therefor'
[patent_app_type] => 1
[patent_app_number] => 9/128503
[patent_app_country] => US
[patent_app_date] => 1998-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6795
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/237/06237101.pdf
[firstpage_image] =>[orig_patent_app_number] => 128503
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/128503 | Microprocessor including controller for reduced power consumption and method therefor | Aug 2, 1998 | Issued |
Array
(
[id] => 4318266
[patent_doc_number] => 06185690
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Portable computer having a radio function and related method'
[patent_app_type] => 1
[patent_app_number] => 9/124028
[patent_app_country] => US
[patent_app_date] => 1998-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3238
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/185/06185690.pdf
[firstpage_image] =>[orig_patent_app_number] => 124028
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/124028 | Portable computer having a radio function and related method | Jul 28, 1998 | Issued |