Search

Sumati Lefkowitz

Supervisory Patent Examiner (ID: 15758, Phone: (571)272-3638 , Office: P/2666 )

Most Active Art Unit
2781
Art Unit(s)
2662, 2781, 2666, 2629, 2305, 2672, 2189, 2112, 2694, 2181
Total Applications
514
Issued Applications
375
Pending Applications
24
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4100407 [patent_doc_number] => 06055642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Single chip clock control circuit operating independently of CPU control' [patent_app_type] => 1 [patent_app_number] => 9/115507 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11447 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055642.pdf [firstpage_image] =>[orig_patent_app_number] => 115507 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/115507
Single chip clock control circuit operating independently of CPU control Jul 14, 1998 Issued
Array ( [id] => 4123794 [patent_doc_number] => 06101569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Computer resources access control apparatus and method' [patent_app_type] => 1 [patent_app_number] => 9/111029 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10910 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101569.pdf [firstpage_image] =>[orig_patent_app_number] => 111029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/111029
Computer resources access control apparatus and method Jul 6, 1998 Issued
Array ( [id] => 4334868 [patent_doc_number] => 06243774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Apparatus program product and method of managing computer resources supporting concurrent maintenance operations' [patent_app_type] => 1 [patent_app_number] => 9/106949 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 14038 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243774.pdf [firstpage_image] =>[orig_patent_app_number] => 106949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/106949
Apparatus program product and method of managing computer resources supporting concurrent maintenance operations Jun 29, 1998 Issued
Array ( [id] => 4178965 [patent_doc_number] => 06115778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method and apparatus for handling interrupts through the use of a vector access signal' [patent_app_type] => 1 [patent_app_number] => 9/100244 [patent_app_country] => US [patent_app_date] => 1998-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4018 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115778.pdf [firstpage_image] =>[orig_patent_app_number] => 100244 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/100244
Method and apparatus for handling interrupts through the use of a vector access signal Jun 18, 1998 Issued
Array ( [id] => 4260661 [patent_doc_number] => 06092208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'System and method for waking a computer having a plurality of power resources from a system state using a data structure' [patent_app_type] => 1 [patent_app_number] => 9/098925 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 14102 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092208.pdf [firstpage_image] =>[orig_patent_app_number] => 098925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098925
System and method for waking a computer having a plurality of power resources from a system state using a data structure Jun 16, 1998 Issued
Array ( [id] => 4194654 [patent_doc_number] => 06085270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Multi-channel, multi-rate isochronous data bus' [patent_app_type] => 1 [patent_app_number] => 9/098655 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5891 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085270.pdf [firstpage_image] =>[orig_patent_app_number] => 098655 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098655
Multi-channel, multi-rate isochronous data bus Jun 16, 1998 Issued
Array ( [id] => 4238684 [patent_doc_number] => 06088748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Personal computer system incorporating an isochronous multi-channel, multi-rate data bus' [patent_app_type] => 1 [patent_app_number] => 9/098642 [patent_app_country] => US [patent_app_date] => 1998-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5867 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088748.pdf [firstpage_image] =>[orig_patent_app_number] => 098642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098642
Personal computer system incorporating an isochronous multi-channel, multi-rate data bus Jun 16, 1998 Issued
Array ( [id] => 4160278 [patent_doc_number] => 06061752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Technique for hot plugging a peripheral controller card containing PCI and SCSI buses on a single connector into a host system board' [patent_app_type] => 1 [patent_app_number] => 9/097493 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4001 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061752.pdf [firstpage_image] =>[orig_patent_app_number] => 097493 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097493
Technique for hot plugging a peripheral controller card containing PCI and SCSI buses on a single connector into a host system board Jun 14, 1998 Issued
Array ( [id] => 4256773 [patent_doc_number] => 06081861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'PCI migration support of ISA adapters' [patent_app_type] => 1 [patent_app_number] => 9/094712 [patent_app_country] => US [patent_app_date] => 1998-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2247 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081861.pdf [firstpage_image] =>[orig_patent_app_number] => 094712 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094712
PCI migration support of ISA adapters Jun 14, 1998 Issued
Array ( [id] => 4177676 [patent_doc_number] => 06105141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method and apparatus for power management of an external cache of a computer system' [patent_app_type] => 1 [patent_app_number] => 9/090644 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4273 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105141.pdf [firstpage_image] =>[orig_patent_app_number] => 090644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090644
Method and apparatus for power management of an external cache of a computer system Jun 3, 1998 Issued
Array ( [id] => 4192302 [patent_doc_number] => 06141717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Microcomputer having bus isolation means for selectively coupling an external bus to either a memory bus or a peripheral bus for testing of memory and peripheral circuits' [patent_app_type] => 1 [patent_app_number] => 9/084592 [patent_app_country] => US [patent_app_date] => 1998-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4884 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141717.pdf [firstpage_image] =>[orig_patent_app_number] => 084592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084592
Microcomputer having bus isolation means for selectively coupling an external bus to either a memory bus or a peripheral bus for testing of memory and peripheral circuits May 26, 1998 Issued
Array ( [id] => 4259487 [patent_doc_number] => 06092134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method and apparatus for locking out a processor in a computer system with a bus that is improperly terminated' [patent_app_type] => 1 [patent_app_number] => 9/083325 [patent_app_country] => US [patent_app_date] => 1998-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4483 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092134.pdf [firstpage_image] =>[orig_patent_app_number] => 083325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/083325
Method and apparatus for locking out a processor in a computer system with a bus that is improperly terminated May 20, 1998 Issued
Array ( [id] => 1501490 [patent_doc_number] => 06405272 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'System and method for arbitration of a plurality of processing modules' [patent_app_type] => B1 [patent_app_number] => 09/079600 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 14 [patent_no_of_words] => 5060 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405272.pdf [firstpage_image] =>[orig_patent_app_number] => 09079600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/079600
System and method for arbitration of a plurality of processing modules May 14, 1998 Issued
Array ( [id] => 4423896 [patent_doc_number] => 06240520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Power on/off control device for computer' [patent_app_type] => 1 [patent_app_number] => 9/093830 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3908 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240520.pdf [firstpage_image] =>[orig_patent_app_number] => 093830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093830
Power on/off control device for computer May 11, 1998 Issued
Array ( [id] => 4292078 [patent_doc_number] => 06247088 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Bridgeless embedded PCI computer system using syncronous dynamic ram architecture' [patent_app_type] => 1 [patent_app_number] => 9/074811 [patent_app_country] => US [patent_app_date] => 1998-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10606 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247088.pdf [firstpage_image] =>[orig_patent_app_number] => 074811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074811
Bridgeless embedded PCI computer system using syncronous dynamic ram architecture May 7, 1998 Issued
Array ( [id] => 4422567 [patent_doc_number] => 06233693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Smart DASD spin-up' [patent_app_type] => 1 [patent_app_number] => 9/073940 [patent_app_country] => US [patent_app_date] => 1998-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233693.pdf [firstpage_image] =>[orig_patent_app_number] => 073940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/073940
Smart DASD spin-up May 5, 1998 Issued
Array ( [id] => 4203925 [patent_doc_number] => 06151655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Computer system deadlock request resolution using timed pulses' [patent_app_type] => 1 [patent_app_number] => 9/070432 [patent_app_country] => US [patent_app_date] => 1998-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7912 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151655.pdf [firstpage_image] =>[orig_patent_app_number] => 070432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070432
Computer system deadlock request resolution using timed pulses Apr 29, 1998 Issued
Array ( [id] => 4177702 [patent_doc_number] => 06105143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Power control device and method of controlling power of peripheral devices of a computer system using a universal serial bus (USB) hub' [patent_app_type] => 1 [patent_app_number] => 9/063928 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3007 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105143.pdf [firstpage_image] =>[orig_patent_app_number] => 063928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063928
Power control device and method of controlling power of peripheral devices of a computer system using a universal serial bus (USB) hub Apr 21, 1998 Issued
Array ( [id] => 6881033 [patent_doc_number] => 20010032321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-18 [patent_title] => 'Power Conservation for a Display Controller in Accordance with the State of Connection or of the Source Power Received by the Display Controller' [patent_app_type] => new [patent_app_number] => 09/055938 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7066 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20010032321.pdf [firstpage_image] =>[orig_patent_app_number] => 09055938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055938
Power Conservation for a Display Controller in Accordance with the State of Connection or of the Source Power Received by the Display Controller Apr 6, 1998 Abandoned
Array ( [id] => 4423688 [patent_doc_number] => 06311290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Methods of reliably allocating, de-allocating, re-allocating, and reclaiming objects in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture' [patent_app_type] => 1 [patent_app_number] => 9/055032 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 19971 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311290.pdf [firstpage_image] =>[orig_patent_app_number] => 055032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055032
Methods of reliably allocating, de-allocating, re-allocating, and reclaiming objects in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture Apr 2, 1998 Issued
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