Sumati Lefkowitz

Array ( [id] => 4403691 [patent_doc_number] => 06263387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'System for automatically configuring a server after hot add of a device' [patent_app_type] => 1 [patent_app_number] => 8/942331 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7878 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263387.pdf [firstpage_image] =>[orig_patent_app_number] => 942331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4109695 [patent_doc_number] => 06134614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method for facilitating the replacement or insertion of devices in a computer system through the use of a graphical user interface' [patent_app_type] => 1 [patent_app_number] => 8/942316 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 7503 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134614.pdf [firstpage_image] =>[orig_patent_app_number] => 942316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4294474 [patent_doc_number] => 06324608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method for hot swapping of network components' [patent_app_type] => 1 [patent_app_number] => 8/943044 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5230 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324608.pdf [firstpage_image] =>[orig_patent_app_number] => 943044 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309867 [patent_doc_number] => 06212585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method of automatically configuring a server after hot add of a device' [patent_app_type] => 1 [patent_app_number] => 8/942319 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7221 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212585.pdf [firstpage_image] =>[orig_patent_app_number] => 942319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4123735 [patent_doc_number] => 06101565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'System for multisized bus coupling in a packet-switched computer system' [patent_app_type] => 1 [patent_app_number] => 8/912772 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4184 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101565.pdf [firstpage_image] =>[orig_patent_app_number] => 912772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3974604 [patent_doc_number] => 05901322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method and apparatus for dynamic control of clocks in a multiple clock processor, particularly for a data cache' [patent_app_type] => 1 [patent_app_number] => 8/908769 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4355 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901322.pdf [firstpage_image] =>[orig_patent_app_number] => 908769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3826276 [patent_doc_number] => 05832247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'PCI card for receiving a GPS signal' [patent_app_type] => 1 [patent_app_number] => 8/903965 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/832/05832247.pdf [firstpage_image] =>[orig_patent_app_number] => 903965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4068022 [patent_doc_number] => 05933616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Multiple bus system bus arbitration according to type of transaction requested and the availability status of the data buffer between the buses' [patent_app_type] => 1 [patent_app_number] => 8/895661 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5726 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933616.pdf [firstpage_image] =>[orig_patent_app_number] => 895661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3997948 [patent_doc_number] => 05949981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Deadlock avoidance in a bridge between a split transaction bus and a single envelope bus' [patent_app_type] => 1 [patent_app_number] => 8/888113 [patent_app_country] => US [patent_app_date] => 1997-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4987 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949981.pdf [firstpage_image] =>[orig_patent_app_number] => 888113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4076180 [patent_doc_number] => 05896516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and apparatus for reducing propagation latency in a high speed crossbar switch' [patent_app_type] => 1 [patent_app_number] => 8/885821 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2539 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896516.pdf [firstpage_image] =>[orig_patent_app_number] => 885821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998473 [patent_doc_number] => 05862387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Method and apparatus for handling bus master and direct memory access (DMA) requests at an I/O controller' [patent_app_type] => 1 [patent_app_number] => 8/884023 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7660 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862387.pdf [firstpage_image] =>[orig_patent_app_number] => 884023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998708 [patent_doc_number] => 05862401 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Programmable central intelligence controller and distributed intelligence network for analog/digital control systems' [patent_app_type] => 1 [patent_app_number] => 8/883869 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 3927 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862401.pdf [firstpage_image] =>[orig_patent_app_number] => 883869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4008780 [patent_doc_number] => 05892972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method of constructing a plug and play compatible bus card which allows for mass production of the bus card' [patent_app_type] => 1 [patent_app_number] => 8/877207 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1816 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892972.pdf [firstpage_image] =>[orig_patent_app_number] => 877207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4088450 [patent_doc_number] => 06070211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Driver/receiver circuitry for enhanced PCI bus with differential signaling' [patent_app_type] => 1 [patent_app_number] => 8/872823 [patent_app_country] => US [patent_app_date] => 1997-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4241 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070211.pdf [firstpage_image] =>[orig_patent_app_number] => 872823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252291 [patent_doc_number] => 06076132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Arbitration method and circuit to increase access without increasing latency' [patent_app_type] => 1 [patent_app_number] => 8/864950 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9294 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076132.pdf [firstpage_image] =>[orig_patent_app_number] => 864950 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3849357 [patent_doc_number] => 05815676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Address bus arbiter for pipelined transactions on a split bus' [patent_app_type] => 1 [patent_app_number] => 8/859392 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4482 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815676.pdf [firstpage_image] =>[orig_patent_app_number] => 859392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3998011 [patent_doc_number] => 05862358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches' [patent_app_type] => 1 [patent_app_number] => 8/856032 [patent_app_country] => US [patent_app_date] => 1997-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2989 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862358.pdf [firstpage_image] =>[orig_patent_app_number] => 856032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3986097 [patent_doc_number] => 05919259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Method and apparatus for supplying power to a CPU using an adaptor card' [patent_app_type] => 1 [patent_app_number] => 8/837480 [patent_app_country] => US [patent_app_date] => 1997-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1846 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/919/05919259.pdf [firstpage_image] =>[orig_patent_app_number] => 837480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3951629 [patent_doc_number] => 05872937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'System for optimizing bus arbitration latency and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/837429 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872937.pdf [firstpage_image] =>[orig_patent_app_number] => 837429 [rel_patent_id] =>[rel_patent_doc_number] =>)