Search

Sumati Lefkowitz

Supervisory Patent Examiner (ID: 13987, Phone: (571)272-3638 , Office: P/2666 )

Most Active Art Unit
2781
Art Unit(s)
2694, 2672, 2189, 2662, 2629, 2305, 2781, 2181, 2112, 2666
Total Applications
519
Issued Applications
375
Pending Applications
30
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4089017 [patent_doc_number] => 06070247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Method and apparatus for controlling power to a multi-media conferencing system using any one of a system power switch and a computer' [patent_app_type] => 1 [patent_app_number] => 8/760120 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 4613 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070247.pdf [firstpage_image] =>[orig_patent_app_number] => 760120 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/760120
Method and apparatus for controlling power to a multi-media conferencing system using any one of a system power switch and a computer Dec 2, 1996 Issued
Array ( [id] => 4057288 [patent_doc_number] => 05875312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Structure and method of performing DMA transfers between memory and I/O devices utilizing a single DMA controller within a notebook and docking station computer system' [patent_app_type] => 1 [patent_app_number] => 8/758803 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 105 [patent_no_of_words] => 92523 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875312.pdf [firstpage_image] =>[orig_patent_app_number] => 758803 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758803
Structure and method of performing DMA transfers between memory and I/O devices utilizing a single DMA controller within a notebook and docking station computer system Dec 2, 1996 Issued
Array ( [id] => 3983871 [patent_doc_number] => 05887144 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches' [patent_app_type] => 1 [patent_app_number] => 8/753116 [patent_app_country] => US [patent_app_date] => 1996-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4597 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/887/05887144.pdf [firstpage_image] =>[orig_patent_app_number] => 753116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753116
Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches Nov 19, 1996 Issued
Array ( [id] => 3870742 [patent_doc_number] => 05706446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Arbitration system for bus requestors with deadlock prevention' [patent_app_type] => 1 [patent_app_number] => 8/747134 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5590 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706446.pdf [firstpage_image] =>[orig_patent_app_number] => 747134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/747134
Arbitration system for bus requestors with deadlock prevention Nov 11, 1996 Issued
Array ( [id] => 3788774 [patent_doc_number] => 05774734 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Variable-voltage CPU voltage regulator' [patent_app_type] => 1 [patent_app_number] => 8/753262 [patent_app_country] => US [patent_app_date] => 1996-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1186 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774734.pdf [firstpage_image] =>[orig_patent_app_number] => 753262 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/753262
Variable-voltage CPU voltage regulator Nov 11, 1996 Issued
Array ( [id] => 3859540 [patent_doc_number] => 05745795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'SCSI connector and Y cable configuration which selectively provides single or dual SCSI channels on a single standard SCSI connector' [patent_app_type] => 1 [patent_app_number] => 8/743091 [patent_app_country] => US [patent_app_date] => 1996-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/745/05745795.pdf [firstpage_image] =>[orig_patent_app_number] => 743091 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/743091
SCSI connector and Y cable configuration which selectively provides single or dual SCSI channels on a single standard SCSI connector Nov 3, 1996 Issued
Array ( [id] => 4040845 [patent_doc_number] => 05884084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Circuit and method for using early reset to prevent CMOS corruption with advanced power supplies' [patent_app_type] => 1 [patent_app_number] => 8/742116 [patent_app_country] => US [patent_app_date] => 1996-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2948 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/884/05884084.pdf [firstpage_image] =>[orig_patent_app_number] => 742116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/742116
Circuit and method for using early reset to prevent CMOS corruption with advanced power supplies Oct 30, 1996 Issued
08/726694 COMPUTER SYSTEM WITH UNATTENDED ON-DEMAND AVAILABILITY Oct 6, 1996 Abandoned
Array ( [id] => 4042417 [patent_doc_number] => 05931930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Processor that indicates system bus ownership in an upgradable multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 8/723667 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4218 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931930.pdf [firstpage_image] =>[orig_patent_app_number] => 723667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723667
Processor that indicates system bus ownership in an upgradable multiprocessor computer system Sep 29, 1996 Issued
Array ( [id] => 4031795 [patent_doc_number] => 05881299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Selectively removing power from multiple display areas of a display unit' [patent_app_type] => 1 [patent_app_number] => 8/721020 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5653 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881299.pdf [firstpage_image] =>[orig_patent_app_number] => 721020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721020
Selectively removing power from multiple display areas of a display unit Sep 25, 1996 Issued
Array ( [id] => 3813066 [patent_doc_number] => 05828854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface' [patent_app_type] => 1 [patent_app_number] => 8/721271 [patent_app_country] => US [patent_app_date] => 1996-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4300 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828854.pdf [firstpage_image] =>[orig_patent_app_number] => 721271 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721271
Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface Sep 25, 1996 Issued
Array ( [id] => 4177296 [patent_doc_number] => 06108726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Reducing the pin count within a switching element through the use of a multiplexer' [patent_app_type] => 1 [patent_app_number] => 8/713489 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2492 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108726.pdf [firstpage_image] =>[orig_patent_app_number] => 713489 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713489
Reducing the pin count within a switching element through the use of a multiplexer Sep 12, 1996 Issued
Array ( [id] => 3997970 [patent_doc_number] => 05862355 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Method and apparatus for overriding bus prioritization scheme' [patent_app_type] => 1 [patent_app_number] => 8/713216 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/862/05862355.pdf [firstpage_image] =>[orig_patent_app_number] => 713216 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713216
Method and apparatus for overriding bus prioritization scheme Sep 11, 1996 Issued
Array ( [id] => 4198734 [patent_doc_number] => 06038620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method and system for optimal high speed match in a high performance controller which ensures an input/output interface stays ahead of a host interface' [patent_app_type] => 1 [patent_app_number] => 8/709931 [patent_app_country] => US [patent_app_date] => 1996-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3300 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038620.pdf [firstpage_image] =>[orig_patent_app_number] => 709931 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/709931
Method and system for optimal high speed match in a high performance controller which ensures an input/output interface stays ahead of a host interface Sep 8, 1996 Issued
Array ( [id] => 3943490 [patent_doc_number] => 05878239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method and apparatus for processing a target retry from a PCI target device to an ISA master devise using a PCI/ISA bridge' [patent_app_type] => 1 [patent_app_number] => 8/705316 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6646 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/878/05878239.pdf [firstpage_image] =>[orig_patent_app_number] => 705316 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705316
Method and apparatus for processing a target retry from a PCI target device to an ISA master devise using a PCI/ISA bridge Aug 28, 1996 Issued
Array ( [id] => 4081360 [patent_doc_number] => 05867676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Reset circuit for a peripheral component interconnect bus' [patent_app_type] => 1 [patent_app_number] => 8/699918 [patent_app_country] => US [patent_app_date] => 1996-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1617 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867676.pdf [firstpage_image] =>[orig_patent_app_number] => 699918 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/699918
Reset circuit for a peripheral component interconnect bus Aug 19, 1996 Issued
Array ( [id] => 3966086 [patent_doc_number] => 05956523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method and apparatus for reducing the number of RS232/RS485 transmission converters required for communicating between a PC and a plurality of instruments' [patent_app_type] => 1 [patent_app_number] => 8/694969 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1451 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956523.pdf [firstpage_image] =>[orig_patent_app_number] => 694969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694969
Method and apparatus for reducing the number of RS232/RS485 transmission converters required for communicating between a PC and a plurality of instruments Aug 8, 1996 Issued
Array ( [id] => 4008878 [patent_doc_number] => 05892977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Apparatus and method for read-accessing write-only registers in a DMAC' [patent_app_type] => 1 [patent_app_number] => 8/694757 [patent_app_country] => US [patent_app_date] => 1996-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892977.pdf [firstpage_image] =>[orig_patent_app_number] => 694757 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/694757
Apparatus and method for read-accessing write-only registers in a DMAC Aug 8, 1996 Issued
Array ( [id] => 3857419 [patent_doc_number] => 05848251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Secondary channel for command information for fibre channel system interface bus' [patent_app_type] => 1 [patent_app_number] => 8/692516 [patent_app_country] => US [patent_app_date] => 1996-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3025 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848251.pdf [firstpage_image] =>[orig_patent_app_number] => 692516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/692516
Secondary channel for command information for fibre channel system interface bus Aug 5, 1996 Issued
Array ( [id] => 3902403 [patent_doc_number] => 05724528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'PCI/ISA bridge having an arrangement for responding to PCI address parity errors for internal PCI slaves in the PCI/ISA bridge' [patent_app_type] => 1 [patent_app_number] => 8/683867 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3725 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724528.pdf [firstpage_image] =>[orig_patent_app_number] => 683867 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/683867
PCI/ISA bridge having an arrangement for responding to PCI address parity errors for internal PCI slaves in the PCI/ISA bridge Jul 18, 1996 Issued
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