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Sumati Lefkowitz

Supervisory Patent Examiner (ID: 15758, Phone: (571)272-3638 , Office: P/2666 )

Most Active Art Unit
2781
Art Unit(s)
2662, 2781, 2666, 2629, 2305, 2672, 2189, 2112, 2694, 2181
Total Applications
514
Issued Applications
375
Pending Applications
24
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
08/443973 ARBITRATION SYSTEM FOR BUS REQUESTORS WITH DEADLOCK PREVENTION May 17, 1995 Abandoned
Array ( [id] => 3700743 [patent_doc_number] => 05644733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-01 [patent_title] => 'Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses' [patent_app_type] => 1 [patent_app_number] => 8/443974 [patent_app_country] => US [patent_app_date] => 1995-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5659 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 374 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/644/05644733.pdf [firstpage_image] =>[orig_patent_app_number] => 443974 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/443974
Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses May 17, 1995 Issued
Array ( [id] => 3641907 [patent_doc_number] => 05687328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Method and apparatus for aligning data for transfer between a source memory and a destination memory over a multibit bus' [patent_app_type] => 1 [patent_app_number] => 8/442551 [patent_app_country] => US [patent_app_date] => 1995-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3443 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/687/05687328.pdf [firstpage_image] =>[orig_patent_app_number] => 442551 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/442551
Method and apparatus for aligning data for transfer between a source memory and a destination memory over a multibit bus May 15, 1995 Issued
08/439030 SYSTEM AND METHOD FOR PROVIDING HIGH SPEED MEMORY ACCESS IN A MULTIPROCESSOR, MULTIMEMORY ENVIRONMENT May 10, 1995 Abandoned
Array ( [id] => 3660735 [patent_doc_number] => 05630145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Method and apparatus for reducing power consumption according to bus activity as determined by bus access times' [patent_app_type] => 1 [patent_app_number] => 8/435351 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2593 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630145.pdf [firstpage_image] =>[orig_patent_app_number] => 435351 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435351
Method and apparatus for reducing power consumption according to bus activity as determined by bus access times May 4, 1995 Issued
Array ( [id] => 3635113 [patent_doc_number] => 05689726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Computer system interface adapter capable of automatic self-configuration and self-diagnosis before operating system initiation' [patent_app_type] => 1 [patent_app_number] => 8/433724 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5510 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689726.pdf [firstpage_image] =>[orig_patent_app_number] => 433724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/433724
Computer system interface adapter capable of automatic self-configuration and self-diagnosis before operating system initiation May 2, 1995 Issued
Array ( [id] => 3675254 [patent_doc_number] => 05625778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Method and apparatus for presenting an access request from a computer system bus to a system resource with reduced latency' [patent_app_type] => 1 [patent_app_number] => 8/434193 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6230 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625778.pdf [firstpage_image] =>[orig_patent_app_number] => 434193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/434193
Method and apparatus for presenting an access request from a computer system bus to a system resource with reduced latency May 2, 1995 Issued
08/432621 DEADLOCK AVOIDANCE IN A BRIDGE BETWEEN A SPLIT-TRANSACTION BUS AND A SINGLE-ENVELOPE BUS May 1, 1995 Abandoned
08/430452 ADDRESS BUS ARBITER FOR PIPELINED TRANSACTIONS ON A SPLIT BUS Apr 27, 1995 Abandoned
Array ( [id] => 3974225 [patent_doc_number] => 05901295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Address and data bus arbiter for pipelined transactions on a split bus' [patent_app_type] => 1 [patent_app_number] => 8/430451 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/901/05901295.pdf [firstpage_image] =>[orig_patent_app_number] => 430451 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430451
Address and data bus arbiter for pipelined transactions on a split bus Apr 27, 1995 Issued
Array ( [id] => 3854417 [patent_doc_number] => 05708783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Data bus arbiter for pipelined transactions on a split bus' [patent_app_type] => 1 [patent_app_number] => 8/430454 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4451 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708783.pdf [firstpage_image] =>[orig_patent_app_number] => 430454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430454
Data bus arbiter for pipelined transactions on a split bus Apr 27, 1995 Issued
08/427027 METHOD AND APPARATUS FOR OPERATING DIGITAL STATIC CMOS COMPONENTS IN A VERY LOW VOLTAGE MODE DURING POWER-DOWN Apr 23, 1995 Abandoned
Array ( [id] => 3702020 [patent_doc_number] => 05664197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller' [patent_app_type] => 1 [patent_app_number] => 8/426825 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7659 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664197.pdf [firstpage_image] =>[orig_patent_app_number] => 426825 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/426825
Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller Apr 20, 1995 Issued
Array ( [id] => 3893857 [patent_doc_number] => 05764926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Supressing in rush current from a power supply during live wire insertion and removal of a circuit board' [patent_app_type] => 1 [patent_app_number] => 8/423214 [patent_app_country] => US [patent_app_date] => 1995-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4555 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/764/05764926.pdf [firstpage_image] =>[orig_patent_app_number] => 423214 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/423214
Supressing in rush current from a power supply during live wire insertion and removal of a circuit board Apr 16, 1995 Issued
Array ( [id] => 3701878 [patent_doc_number] => 05692197 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-25 [patent_title] => 'Method and apparatus for reducing power consumption in a computer network without sacrificing performance' [patent_app_type] => 1 [patent_app_number] => 8/414879 [patent_app_country] => US [patent_app_date] => 1995-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5737 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/692/05692197.pdf [firstpage_image] =>[orig_patent_app_number] => 414879 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/414879
Method and apparatus for reducing power consumption in a computer network without sacrificing performance Mar 30, 1995 Issued
08/406724 ASYNCHRONOUS EXPANSION BUS FOR A COMMUNICATION NETWORK Mar 19, 1995 Abandoned
08/400027 METHOD AND APPARATUS FOR PROVIDING UNATTENDED ON-DEMAND AVAILABILITY OF A COMPUTER SYSTEM Mar 5, 1995 Abandoned
Array ( [id] => 3612052 [patent_doc_number] => 05559968 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Non-conforming PCI bus master timing compensation circuit' [patent_app_type] => 1 [patent_app_number] => 8/398382 [patent_app_country] => US [patent_app_date] => 1995-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5319 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559968.pdf [firstpage_image] =>[orig_patent_app_number] => 398382 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/398382
Non-conforming PCI bus master timing compensation circuit Mar 2, 1995 Issued
Array ( [id] => 3708182 [patent_doc_number] => 05596757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'System and method for selectively providing termination power to a SCSI bus terminator from a host device' [patent_app_type] => 1 [patent_app_number] => 8/390749 [patent_app_country] => US [patent_app_date] => 1995-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5074 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/596/05596757.pdf [firstpage_image] =>[orig_patent_app_number] => 390749 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/390749
System and method for selectively providing termination power to a SCSI bus terminator from a host device Feb 15, 1995 Issued
Array ( [id] => 3661417 [patent_doc_number] => 05606672 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface' [patent_app_type] => 1 [patent_app_number] => 8/380020 [patent_app_country] => US [patent_app_date] => 1995-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4300 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606672.pdf [firstpage_image] =>[orig_patent_app_number] => 380020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/380020
Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface Jan 26, 1995 Issued
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