Search

Sumati Lefkowitz

Supervisory Patent Examiner (ID: 2522, Phone: (571)272-3638 , Office: P/2666 )

Most Active Art Unit
2781
Art Unit(s)
2781, 2181, 2662, 2112, 2629, 2672, 2666, 2305, 2694, 2189
Total Applications
514
Issued Applications
375
Pending Applications
24
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10590381 [patent_doc_number] => 09312001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-12 [patent_title] => 'Writing and verifying circuit for a resistive memory and method for writing and verifying a resistive memory' [patent_app_type] => utility [patent_app_number] => 14/623507 [patent_app_country] => US [patent_app_date] => 2015-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4043 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14623507 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/623507
Writing and verifying circuit for a resistive memory and method for writing and verifying a resistive memory Feb 16, 2015 Issued
Array ( [id] => 10817216 [patent_doc_number] => 20160163378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'TIME DIVISION MULTIPLEXED MULTIPORT MEMORY' [patent_app_type] => utility [patent_app_number] => 14/622063 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12155 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622063 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622063
Time division multiplexed multiport memory Feb 12, 2015 Issued
Array ( [id] => 10624212 [patent_doc_number] => 09343160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Erase verify in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/619857 [patent_app_country] => US [patent_app_date] => 2015-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 39 [patent_no_of_words] => 22651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14619857 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/619857
Erase verify in non-volatile memory Feb 10, 2015 Issued
Array ( [id] => 10329273 [patent_doc_number] => 20150214277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'Small-Grain Three-Dimensional Memory' [patent_app_type] => utility [patent_app_number] => 14/614434 [patent_app_country] => US [patent_app_date] => 2015-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14614434 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/614434
Small-grain three-dimensional memory Feb 4, 2015 Issued
Array ( [id] => 10576800 [patent_doc_number] => 09299450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-29 [patent_title] => 'Adaptive increase in control gate voltage of a dummy memory cell to compensate for inadvertent programming' [patent_app_type] => utility [patent_app_number] => 14/612601 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 51 [patent_no_of_words] => 19435 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612601 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612601
Adaptive increase in control gate voltage of a dummy memory cell to compensate for inadvertent programming Feb 2, 2015 Issued
Array ( [id] => 10264821 [patent_doc_number] => 20150149817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'MANAGING NON-VOLATILE MEDIA' [patent_app_type] => utility [patent_app_number] => 14/611088 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 39410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14611088 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/611088
System, method, and apparatus for improving the utility of storage media Jan 29, 2015 Issued
Array ( [id] => 10551113 [patent_doc_number] => 09275744 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-01 [patent_title] => 'Method of restoring a flash memory in an integrated circuit chip package by addition of heat and an electric field' [patent_app_type] => utility [patent_app_number] => 14/608243 [patent_app_country] => US [patent_app_date] => 2015-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14608243 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/608243
Method of restoring a flash memory in an integrated circuit chip package by addition of heat and an electric field Jan 28, 2015 Issued
Array ( [id] => 10125035 [patent_doc_number] => 09159401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Semiconductor device having hierarchical bit line structure' [patent_app_type] => utility [patent_app_number] => 14/597471 [patent_app_country] => US [patent_app_date] => 2015-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6847 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14597471 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/597471
Semiconductor device having hierarchical bit line structure Jan 14, 2015 Issued
Array ( [id] => 10624203 [patent_doc_number] => 09343151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-17 [patent_title] => 'Resistive random access memory and method of resetting a resistive random access memory' [patent_app_type] => utility [patent_app_number] => 14/593075 [patent_app_country] => US [patent_app_date] => 2015-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14593075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/593075
Resistive random access memory and method of resetting a resistive random access memory Jan 8, 2015 Issued
Array ( [id] => 10224873 [patent_doc_number] => 20150109866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'DATA PATHS USING A FIRST SIGNAL TO CAPTURE DATA AND A SECOND SIGNAL TO OUTPUT DATA AND METHODS FOR PROVIDING DATA' [patent_app_type] => utility [patent_app_number] => 14/578927 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3700 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14578927 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/578927
Data paths using a first signal to capture data and a second signal to output data and methods for providing data Dec 21, 2014 Issued
Array ( [id] => 10645116 [patent_doc_number] => 09361989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-07 [patent_title] => 'Memory device and data erasing method thereof' [patent_app_type] => utility [patent_app_number] => 14/571351 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14571351 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/571351
Memory device and data erasing method thereof Dec 15, 2014 Issued
Array ( [id] => 10673824 [patent_doc_number] => 20160019969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/572717 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572717 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/572717
Semiconductor memory apparatus and method for reading data from the same Dec 15, 2014 Issued
Array ( [id] => 10377628 [patent_doc_number] => 20150262635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'LATCH CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/556917 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7475 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14556917 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/556917
LATCH CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME Nov 30, 2014 Abandoned
Array ( [id] => 10631325 [patent_doc_number] => 09349479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-24 [patent_title] => 'Boundary word line operation in nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 14/546591 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 10660 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14546591 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/546591
Boundary word line operation in nonvolatile memory Nov 17, 2014 Issued
Array ( [id] => 9929898 [patent_doc_number] => 20150078090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => '3D Non-Volatile Storage With Transistor Decoding Structure' [patent_app_type] => utility [patent_app_number] => 14/543342 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 79 [patent_no_of_words] => 32388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/543342
3D non-volatile storage with transistor decoding structure Nov 16, 2014 Issued
Array ( [id] => 10531822 [patent_doc_number] => 09257971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Integrated circuit, method for driving the same, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/541305 [patent_app_country] => US [patent_app_date] => 2014-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 20543 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14541305 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/541305
Integrated circuit, method for driving the same, and semiconductor device Nov 13, 2014 Issued
Array ( [id] => 10659297 [patent_doc_number] => 20160005441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'CHARGE PUMP SYSTEM AND ASSOCIATED CONTROL METHOD FOR MEMORY CELL ARRAY' [patent_app_type] => utility [patent_app_number] => 14/539201 [patent_app_country] => US [patent_app_date] => 2014-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5314 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14539201 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/539201
Low power consumption charge pump system and associated control circuit and method for non-volatile memory cell array Nov 11, 2014 Issued
Array ( [id] => 10544273 [patent_doc_number] => 09269405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-23 [patent_title] => 'Switchable bit-line pair semiconductor memory' [patent_app_type] => utility [patent_app_number] => 14/533065 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2772 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14533065 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/533065
Switchable bit-line pair semiconductor memory Nov 3, 2014 Issued
Array ( [id] => 9900192 [patent_doc_number] => 20150055390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'CONTENT ADDRESSABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/529074 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 20742 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14529074 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/529074
Content addressable memory Oct 29, 2014 Issued
Array ( [id] => 10053299 [patent_doc_number] => 09093180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 14/524503 [patent_app_country] => US [patent_app_date] => 2014-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 7929 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14524503 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/524503
Semiconductor memory device Oct 26, 2014 Issued
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