Search

Sumati Lefkowitz

Supervisory Patent Examiner (ID: 18486, Phone: (571)272-3638 , Office: P/2666 )

Most Active Art Unit
2781
Art Unit(s)
2112, 2662, 2666, 2189, 2181, 2305, 2781, 2672, 2694, 2629
Total Applications
516
Issued Applications
375
Pending Applications
28
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6265243 [patent_doc_number] => 20020188780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method and apparatus for accelerating detection of serial bus device speed signals' [patent_app_type] => new [patent_app_number] => 10/214285 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3646 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20020188780.pdf [firstpage_image] =>[orig_patent_app_number] => 10214285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/214285
Method and apparatus for accelerating detection of serial bus device speed signals Aug 4, 2002 Issued
Array ( [id] => 1177807 [patent_doc_number] => 06760849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Event initiation bus and associated fault protection for a telecommunications device' [patent_app_type] => B1 [patent_app_number] => 10/211647 [patent_app_country] => US [patent_app_date] => 2002-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760849.pdf [firstpage_image] =>[orig_patent_app_number] => 10211647 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211647
Event initiation bus and associated fault protection for a telecommunications device Jul 31, 2002 Issued
Array ( [id] => 1100340 [patent_doc_number] => 06823412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'System and method for arbitration of a plurality of processing modules' [patent_app_type] => B2 [patent_app_number] => 10/166216 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 5002 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823412.pdf [firstpage_image] =>[orig_patent_app_number] => 10166216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/166216
System and method for arbitration of a plurality of processing modules Jun 9, 2002 Issued
Array ( [id] => 6554140 [patent_doc_number] => 20020194418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'System for multisized bus coupling in a packet-switched computer system' [patent_app_type] => new [patent_app_number] => 10/135555 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4217 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20020194418.pdf [firstpage_image] =>[orig_patent_app_number] => 10135555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135555
System for multisized bus coupling in a packet-switched computer system Apr 29, 2002 Abandoned
Array ( [id] => 7610052 [patent_doc_number] => 06842807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method and apparatus for deprioritizing a high priority client' [patent_app_type] => utility [patent_app_number] => 10/077838 [patent_app_country] => US [patent_app_date] => 2002-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2555 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842807.pdf [firstpage_image] =>[orig_patent_app_number] => 10077838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/077838
Method and apparatus for deprioritizing a high priority client Feb 14, 2002 Issued
Array ( [id] => 1240827 [patent_doc_number] => 06691196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'First-level removable module having bar code I/O and second-level removable memory' [patent_app_type] => B2 [patent_app_number] => 10/036468 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 4538 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691196.pdf [firstpage_image] =>[orig_patent_app_number] => 10036468 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036468
First-level removable module having bar code I/O and second-level removable memory Jan 6, 2002 Issued
Array ( [id] => 1088506 [patent_doc_number] => 06832269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Apparatus and method for supporting multiple graphics adapters in a computer system' [patent_app_type] => B2 [patent_app_number] => 10/035253 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 2545 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832269.pdf [firstpage_image] =>[orig_patent_app_number] => 10035253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035253
Apparatus and method for supporting multiple graphics adapters in a computer system Jan 3, 2002 Issued
Array ( [id] => 6762971 [patent_doc_number] => 20030126333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Daisy chain latency reduction' [patent_app_type] => new [patent_app_number] => 10/038325 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2782 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126333.pdf [firstpage_image] =>[orig_patent_app_number] => 10038325 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038325
Daisy chain latency reduction Jan 1, 2002 Issued
Array ( [id] => 7626851 [patent_doc_number] => 06807593 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Enhanced bus architecture for posted read operation between masters and slaves' [patent_app_type] => B1 [patent_app_number] => 10/036820 [patent_app_country] => US [patent_app_date] => 2001-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3764 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807593.pdf [firstpage_image] =>[orig_patent_app_number] => 10036820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036820
Enhanced bus architecture for posted read operation between masters and slaves Oct 31, 2001 Issued
Array ( [id] => 6656115 [patent_doc_number] => 20030009613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method of interconnecting network components' [patent_app_type] => new [patent_app_number] => 10/016296 [patent_app_country] => US [patent_app_date] => 2001-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6306 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20030009613.pdf [firstpage_image] =>[orig_patent_app_number] => 10016296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016296
Method of providing an interface to a plurality of peripheral devices using bus adapter chips Oct 29, 2001 Issued
Array ( [id] => 6397032 [patent_doc_number] => 20020181449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method and apparatus for determining connections in a crossbar switch' [patent_app_type] => new [patent_app_number] => 10/032825 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6886 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20020181449.pdf [firstpage_image] =>[orig_patent_app_number] => 10032825 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032825
Method and apparatus for determining connections in a crossbar switch Oct 23, 2001 Issued
Array ( [id] => 6793381 [patent_doc_number] => 20030088725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Centrally distributed serial bus' [patent_app_type] => new [patent_app_number] => 10/037589 [patent_app_country] => US [patent_app_date] => 2001-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3587 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088725.pdf [firstpage_image] =>[orig_patent_app_number] => 10037589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037589
Centrally distributed serial bus Oct 22, 2001 Issued
Array ( [id] => 1143429 [patent_doc_number] => 06785760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Performance of a PCI-X to infiniband bridge' [patent_app_type] => B2 [patent_app_number] => 10/033487 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6473 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785760.pdf [firstpage_image] =>[orig_patent_app_number] => 10033487 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033487
Performance of a PCI-X to infiniband bridge Oct 18, 2001 Issued
Array ( [id] => 6814957 [patent_doc_number] => 20030074507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method and apparatus for scheduling a resource to meet quality-of-service restrictions' [patent_app_type] => new [patent_app_number] => 09/977602 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2738 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074507.pdf [firstpage_image] =>[orig_patent_app_number] => 09977602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977602
Method and apparatus for scheduling a resource to meet quality-of-service restrictions Oct 11, 2001 Issued
09/942818 Method and apparatus for displaying information in a display screen region identified by permanent printing Aug 28, 2001 Abandoned
Array ( [id] => 7618499 [patent_doc_number] => 06944691 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Architecture that converts a half-duplex bus to a full-duplex bus while keeping the bandwidth of the bus constant' [patent_app_type] => utility [patent_app_number] => 09/915794 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3244 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944691.pdf [firstpage_image] =>[orig_patent_app_number] => 09915794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915794
Architecture that converts a half-duplex bus to a full-duplex bus while keeping the bandwidth of the bus constant Jul 25, 2001 Issued
Array ( [id] => 1085011 [patent_doc_number] => 06834321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-21 [patent_title] => 'Communication method of a serially connected electronic apparatus' [patent_app_type] => B2 [patent_app_number] => 09/907673 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4971 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/834/06834321.pdf [firstpage_image] =>[orig_patent_app_number] => 09907673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907673
Communication method of a serially connected electronic apparatus Jul 18, 2001 Issued
Array ( [id] => 7626850 [patent_doc_number] => 06807594 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Randomized arbiters for eliminating congestion' [patent_app_type] => B1 [patent_app_number] => 09/905071 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3780 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807594.pdf [firstpage_image] =>[orig_patent_app_number] => 09905071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905071
Randomized arbiters for eliminating congestion Jul 15, 2001 Issued
Array ( [id] => 1314234 [patent_doc_number] => 06622195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Interface switching apparatus and switching control method' [patent_app_type] => B2 [patent_app_number] => 09/875990 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6413 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622195.pdf [firstpage_image] =>[orig_patent_app_number] => 09875990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/875990
Interface switching apparatus and switching control method Jun 7, 2001 Issued
Array ( [id] => 5830524 [patent_doc_number] => 20020069372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Process and apparatus for reducing power usage in microprocessor devices according to the type of activity performed by the microprocessor' [patent_app_type] => new [patent_app_number] => 09/873764 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3862 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069372.pdf [firstpage_image] =>[orig_patent_app_number] => 09873764 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873764
Process and apparatus for reducing power usage in microprocessor devices according to the type of activity performed by the microprocessor Jun 3, 2001 Issued
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