
Sumati Lefkowitz
Supervisory Patent Examiner (ID: 15758, Phone: (571)272-3638 , Office: P/2666 )
| Most Active Art Unit | 2781 |
| Art Unit(s) | 2662, 2781, 2666, 2629, 2305, 2672, 2189, 2112, 2694, 2181 |
| Total Applications | 514 |
| Issued Applications | 375 |
| Pending Applications | 24 |
| Abandoned Applications | 115 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1169743
[patent_doc_number] => 06766403
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-20
[patent_title] => 'CPU system with high-speed peripheral LSI circuit'
[patent_app_type] => B2
[patent_app_number] => 09/850235
[patent_app_country] => US
[patent_app_date] => 2001-05-07
[patent_effective_date] => 0000-00-00
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[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/766/06766403.pdf
[firstpage_image] =>[orig_patent_app_number] => 09850235
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/850235 | CPU system with high-speed peripheral LSI circuit | May 6, 2001 | Issued |
Array
(
[id] => 6579860
[patent_doc_number] => 20020166019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-07
[patent_title] => 'Method and apparatus for interfacing a bus with an external device'
[patent_app_type] => new
[patent_app_number] => 09/846959
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[patent_app_date] => 2001-05-01
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[firstpage_image] =>[orig_patent_app_number] => 09846959
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/846959 | Method and apparatus for interfacing a bus with an external device | Apr 30, 2001 | Abandoned |
Array
(
[id] => 1020866
[patent_doc_number] => 06892256
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[patent_kind] => B1
[patent_issue_date] => 2005-05-10
[patent_title] => 'Automated system for storing revision information from slave programmable devices in a master programmable device'
[patent_app_type] => utility
[patent_app_number] => 09/847558
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[firstpage_image] =>[orig_patent_app_number] => 09847558
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/847558 | Automated system for storing revision information from slave programmable devices in a master programmable device | Apr 30, 2001 | Issued |
Array
(
[id] => 5791435
[patent_doc_number] => 20020161953
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation'
[patent_app_type] => new
[patent_app_number] => 09/845455
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/845455 | Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation | Apr 29, 2001 | Issued |
Array
(
[id] => 5791400
[patent_doc_number] => 20020161938
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[patent_issue_date] => 2002-10-31
[patent_title] => 'Increasing control information from a single general purpose input/output (GPIO) mechanism'
[patent_app_type] => new
[patent_app_number] => 09/844178
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/844178 | Increasing control information from a single general purpose input/output (GPIO) mechanism | Apr 26, 2001 | Issued |
Array
(
[id] => 1161305
[patent_doc_number] => 06775730
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[patent_issue_date] => 2004-08-10
[patent_title] => 'System and method for implementing a flexible interrupt mechanism'
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[patent_app_number] => 09/838102
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/838102 | System and method for implementing a flexible interrupt mechanism | Apr 17, 2001 | Issued |
Array
(
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[patent_issue_date] => 2004-03-02
[patent_title] => 'Selectively operating a host\'s device controller in a first mode or a second mode'
[patent_app_type] => B1
[patent_app_number] => 09/820727
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[firstpage_image] =>[orig_patent_app_number] => 09820727
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/820727 | Selectively operating a host's device controller in a first mode or a second mode | Mar 29, 2001 | Issued |
Array
(
[id] => 1027617
[patent_doc_number] => 06886062
[patent_country] => US
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[patent_issue_date] => 2005-04-26
[patent_title] => 'Method and apparatus for improving time constraints and extending limited length cables in a multiple-speed bus'
[patent_app_type] => utility
[patent_app_number] => 09/823455
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/823455 | Method and apparatus for improving time constraints and extending limited length cables in a multiple-speed bus | Mar 29, 2001 | Issued |
Array
(
[id] => 1260394
[patent_doc_number] => 06668294
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[patent_issue_date] => 2003-12-23
[patent_title] => 'Data corruption avoidance on a backplane bus adapted to receive bus controller cards of different types'
[patent_app_type] => B1
[patent_app_number] => 09/810964
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/810964 | Data corruption avoidance on a backplane bus adapted to receive bus controller cards of different types | Mar 16, 2001 | Issued |
Array
(
[id] => 1250218
[patent_doc_number] => 06675242
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[patent_issue_date] => 2004-01-06
[patent_title] => 'Communication bus controller including designation of primary and secondary status according to slot position'
[patent_app_type] => B2
[patent_app_number] => 09/811196
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[patent_app_date] => 2001-03-17
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Array
(
[id] => 1243081
[patent_doc_number] => 06684283
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[patent_issue_date] => 2004-01-27
[patent_title] => 'Method for interfacing a cardbay card to the host system by indicating a 16-bit or cardbus PC card insertion to host software'
[patent_app_type] => B1
[patent_app_number] => 09/804802
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Array
(
[id] => 6896242
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[patent_title] => 'Mode-switchable PC card and PC card input/output control device'
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Array
(
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[patent_title] => 'Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources'
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Array
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Array
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Array
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Array
(
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