Search

Sumati Lefkowitz

Supervisory Patent Examiner (ID: 15758, Phone: (571)272-3638 , Office: P/2666 )

Most Active Art Unit
2781
Art Unit(s)
2662, 2781, 2666, 2629, 2305, 2672, 2189, 2112, 2694, 2181
Total Applications
514
Issued Applications
375
Pending Applications
24
Abandoned Applications
115

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1169743 [patent_doc_number] => 06766403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'CPU system with high-speed peripheral LSI circuit' [patent_app_type] => B2 [patent_app_number] => 09/850235 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3179 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766403.pdf [firstpage_image] =>[orig_patent_app_number] => 09850235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850235
CPU system with high-speed peripheral LSI circuit May 6, 2001 Issued
Array ( [id] => 6579860 [patent_doc_number] => 20020166019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-07 [patent_title] => 'Method and apparatus for interfacing a bus with an external device' [patent_app_type] => new [patent_app_number] => 09/846959 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3829 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20020166019.pdf [firstpage_image] =>[orig_patent_app_number] => 09846959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/846959
Method and apparatus for interfacing a bus with an external device Apr 30, 2001 Abandoned
Array ( [id] => 1020866 [patent_doc_number] => 06892256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Automated system for storing revision information from slave programmable devices in a master programmable device' [patent_app_type] => utility [patent_app_number] => 09/847558 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2284 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892256.pdf [firstpage_image] =>[orig_patent_app_number] => 09847558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847558
Automated system for storing revision information from slave programmable devices in a master programmable device Apr 30, 2001 Issued
Array ( [id] => 5791435 [patent_doc_number] => 20020161953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation' [patent_app_type] => new [patent_app_number] => 09/845455 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6310 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161953.pdf [firstpage_image] =>[orig_patent_app_number] => 09845455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845455
Bus arbitrator supporting multiple isochronous streams in a split transactional unidirectional bus architecture and method of operation Apr 29, 2001 Issued
Array ( [id] => 5791400 [patent_doc_number] => 20020161938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Increasing control information from a single general purpose input/output (GPIO) mechanism' [patent_app_type] => new [patent_app_number] => 09/844178 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1815 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161938.pdf [firstpage_image] =>[orig_patent_app_number] => 09844178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844178
Increasing control information from a single general purpose input/output (GPIO) mechanism Apr 26, 2001 Issued
Array ( [id] => 1161305 [patent_doc_number] => 06775730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'System and method for implementing a flexible interrupt mechanism' [patent_app_type] => B2 [patent_app_number] => 09/838102 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6850 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/775/06775730.pdf [firstpage_image] =>[orig_patent_app_number] => 09838102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838102
System and method for implementing a flexible interrupt mechanism Apr 17, 2001 Issued
Array ( [id] => 1229032 [patent_doc_number] => 06701402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Selectively operating a host\'s device controller in a first mode or a second mode' [patent_app_type] => B1 [patent_app_number] => 09/820727 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701402.pdf [firstpage_image] =>[orig_patent_app_number] => 09820727 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/820727
Selectively operating a host's device controller in a first mode or a second mode Mar 29, 2001 Issued
Array ( [id] => 1027617 [patent_doc_number] => 06886062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Method and apparatus for improving time constraints and extending limited length cables in a multiple-speed bus' [patent_app_type] => utility [patent_app_number] => 09/823455 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4458 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/886/06886062.pdf [firstpage_image] =>[orig_patent_app_number] => 09823455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823455
Method and apparatus for improving time constraints and extending limited length cables in a multiple-speed bus Mar 29, 2001 Issued
Array ( [id] => 1260394 [patent_doc_number] => 06668294 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Data corruption avoidance on a backplane bus adapted to receive bus controller cards of different types' [patent_app_type] => B1 [patent_app_number] => 09/810964 [patent_app_country] => US [patent_app_date] => 2001-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7559 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668294.pdf [firstpage_image] =>[orig_patent_app_number] => 09810964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810964
Data corruption avoidance on a backplane bus adapted to receive bus controller cards of different types Mar 16, 2001 Issued
Array ( [id] => 1250218 [patent_doc_number] => 06675242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Communication bus controller including designation of primary and secondary status according to slot position' [patent_app_type] => B2 [patent_app_number] => 09/811196 [patent_app_country] => US [patent_app_date] => 2001-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8039 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675242.pdf [firstpage_image] =>[orig_patent_app_number] => 09811196 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811196
Communication bus controller including designation of primary and secondary status according to slot position Mar 16, 2001 Issued
Array ( [id] => 1243081 [patent_doc_number] => 06684283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Method for interfacing a cardbay card to the host system by indicating a 16-bit or cardbus PC card insertion to host software' [patent_app_type] => B1 [patent_app_number] => 09/804802 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2464 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684283.pdf [firstpage_image] =>[orig_patent_app_number] => 09804802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804802
Method for interfacing a cardbay card to the host system by indicating a 16-bit or cardbus PC card insertion to host software Mar 12, 2001 Issued
Array ( [id] => 6896242 [patent_doc_number] => 20010027032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Mode-switchable PC card and PC card input/output control device' [patent_app_type] => new [patent_app_number] => 09/797533 [patent_app_country] => US [patent_app_date] => 2001-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3944 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20010027032.pdf [firstpage_image] =>[orig_patent_app_number] => 09797533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/797533
Mode-switchable PC card and PC card input/output control device Feb 28, 2001 Abandoned
Array ( [id] => 1030644 [patent_doc_number] => 06883104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources' [patent_app_type] => utility [patent_app_number] => 09/789182 [patent_app_country] => US [patent_app_date] => 2001-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3852 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/883/06883104.pdf [firstpage_image] =>[orig_patent_app_number] => 09789182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/789182
Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources Feb 19, 2001 Issued
Array ( [id] => 6988672 [patent_doc_number] => 20010037424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Snoop phase in a highly pipelined bus architecture' [patent_app_type] => new [patent_app_number] => 09/783784 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18695 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20010037424.pdf [firstpage_image] =>[orig_patent_app_number] => 09783784 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783784
Snoop phase in a highly pipelined bus architecture Feb 13, 2001 Issued
Array ( [id] => 1196885 [patent_doc_number] => 06732212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-04 [patent_title] => 'Launch raw packet on remote interrupt' [patent_app_type] => B2 [patent_app_number] => 09/785071 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3998 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732212.pdf [firstpage_image] =>[orig_patent_app_number] => 09785071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785071
Launch raw packet on remote interrupt Feb 13, 2001 Issued
Array ( [id] => 7095051 [patent_doc_number] => 20010034803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Connecting a hand-held device to peripheral devices' [patent_app_type] => new [patent_app_number] => 09/780937 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4143 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034803.pdf [firstpage_image] =>[orig_patent_app_number] => 09780937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780937
Connecting a hand-held device to peripheral devices Feb 8, 2001 Abandoned
Array ( [id] => 6686281 [patent_doc_number] => 20030030004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Shared memory control between detector framing node and processor' [patent_app_type] => new [patent_app_number] => 09/774554 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 47730 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20030030004.pdf [firstpage_image] =>[orig_patent_app_number] => 09774554 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774554
Shared memory control between detector framing node and processor Jan 30, 2001 Issued
Array ( [id] => 1291727 [patent_doc_number] => 06643724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method and apparatus for interrupt routing of PCI adapters via device address mapping' [patent_app_type] => B2 [patent_app_number] => 09/748980 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2392 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643724.pdf [firstpage_image] =>[orig_patent_app_number] => 09748980 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748980
Method and apparatus for interrupt routing of PCI adapters via device address mapping Dec 26, 2000 Issued
Array ( [id] => 6085465 [patent_doc_number] => 20020083254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'System and method of implementing interrupts in a computer processing system having a communication fabric comprising a plurality of point-to-point links' [patent_app_type] => new [patent_app_number] => 09/746970 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15484 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083254.pdf [firstpage_image] =>[orig_patent_app_number] => 09746970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746970
System and method of implementing interrupts in a computer processing system having a communication fabric comprising a plurality of point-to-point links Dec 21, 2000 Abandoned
Array ( [id] => 7630006 [patent_doc_number] => 06636933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Data storage system having crossbar switch with multi-staged routing' [patent_app_type] => B1 [patent_app_number] => 09/745814 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 47 [patent_no_of_words] => 26409 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636933.pdf [firstpage_image] =>[orig_patent_app_number] => 09745814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745814
Data storage system having crossbar switch with multi-staged routing Dec 20, 2000 Issued
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