Sumati Lefkowitz

Array ( [id] => 1112130 [patent_doc_number] => 06810452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Method and system for quarantine during bus topology configuration' [patent_app_type] => B1 [patent_app_number] => 09/531080 [patent_app_country] => US [patent_app_date] => 2000-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 12925 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810452.pdf [firstpage_image] =>[orig_patent_app_number] => 09531080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1339045 [patent_doc_number] => 06601124 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Universal interface for selectively coupling to a computer port type and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/503315 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3265 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601124.pdf [firstpage_image] =>[orig_patent_app_number] => 09503315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1420965 [patent_doc_number] => 06542952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'PCI computer system having a transition module and method of operation' [patent_app_type] => B1 [patent_app_number] => 09/499814 [patent_app_country] => US [patent_app_date] => 2000-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4594 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542952.pdf [firstpage_image] =>[orig_patent_app_number] => 09499814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1411321 [patent_doc_number] => 06553445 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method and apparatus for reducing noise associated with switched outputs' [patent_app_type] => B1 [patent_app_number] => 09/498586 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4312 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553445.pdf [firstpage_image] =>[orig_patent_app_number] => 09498586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645913 [patent_doc_number] => 06477610 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Reordering responses on a data bus based on size of response' [patent_app_type] => B1 [patent_app_number] => 09/499059 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5898 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477610.pdf [firstpage_image] =>[orig_patent_app_number] => 09499059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1196896 [patent_doc_number] => 06732213 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Multiple processor computer' [patent_app_type] => B1 [patent_app_number] => 09/496392 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2117 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732213.pdf [firstpage_image] =>[orig_patent_app_number] => 09496392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1400699 [patent_doc_number] => 06564276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Access restriction of environmental circuits' [patent_app_type] => B1 [patent_app_number] => 09/491073 [patent_app_country] => US [patent_app_date] => 2000-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4476 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564276.pdf [firstpage_image] =>[orig_patent_app_number] => 09491073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1138876 [patent_doc_number] => 06789149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Scheme to detect correct plug-in function modules in computers' [patent_app_type] => B1 [patent_app_number] => 09/491288 [patent_app_country] => US [patent_app_date] => 2000-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3600 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789149.pdf [firstpage_image] =>[orig_patent_app_number] => 09491288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4381008 [patent_doc_number] => 06256693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Master/slave data bus employing undirectional address and data lines and request/acknowledge signaling' [patent_app_type] => 1 [patent_app_number] => 9/464262 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3475 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256693.pdf [firstpage_image] =>[orig_patent_app_number] => 464262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1210326 [patent_doc_number] => 06718424 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Bridge circuit for use in a computing platform' [patent_app_type] => B1 [patent_app_number] => 09/458611 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5588 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718424.pdf [firstpage_image] =>[orig_patent_app_number] => 09458611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309882 [patent_doc_number] => 06212586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Hot-swappable high speed point-to-point interface' [patent_app_type] => 1 [patent_app_number] => 9/456659 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4243 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212586.pdf [firstpage_image] =>[orig_patent_app_number] => 456659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1196849 [patent_doc_number] => 06732200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Absorbing jitter during data transmission between applications operating at different frequencies' [patent_app_type] => B1 [patent_app_number] => 09/442350 [patent_app_country] => US [patent_app_date] => 1999-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8453 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732200.pdf [firstpage_image] =>[orig_patent_app_number] => 09442350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1456677 [patent_doc_number] => 06457086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for accelerating detection of serial bus device speed signals' [patent_app_type] => B1 [patent_app_number] => 09/441390 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3727 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457086.pdf [firstpage_image] =>[orig_patent_app_number] => 09441390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418553 [patent_doc_number] => 06546448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and apparatus for arbitrating access to a PCI bus by a plurality of functions in a multi-function master' [patent_app_type] => B1 [patent_app_number] => 09/440764 [patent_app_country] => US [patent_app_date] => 1999-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7009 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546448.pdf [firstpage_image] =>[orig_patent_app_number] => 09440764 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424337 [patent_doc_number] => 06266713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Field upgradeable dynamic data exchanger server' [patent_app_type] => 1 [patent_app_number] => 9/405560 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 10156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266713.pdf [firstpage_image] =>[orig_patent_app_number] => 405560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1186325 [patent_doc_number] => 06742074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Bus to system memory delayed read processing' [patent_app_type] => B2 [patent_app_number] => 09/386808 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2413 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742074.pdf [firstpage_image] =>[orig_patent_app_number] => 09386808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1416802 [patent_doc_number] => 06532512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Selectively coupling an upstream terminal to a USB hub circuit in accordance with a video sync signal' [patent_app_type] => B1 [patent_app_number] => 09/384738 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2641 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532512.pdf [firstpage_image] =>[orig_patent_app_number] => 09384738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1311135 [patent_doc_number] => 06625683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Automatic early PCI transaction retry' [patent_app_type] => B1 [patent_app_number] => 09/379018 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6784 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625683.pdf [firstpage_image] =>[orig_patent_app_number] => 09379018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1573716 [patent_doc_number] => 06499074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Redirecting I/O address holes' [patent_app_type] => B1 [patent_app_number] => 09/379019 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4319 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499074.pdf [firstpage_image] =>[orig_patent_app_number] => 09379019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7645917 [patent_doc_number] => 06477606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Bus system and a master device that stabilizes bus electric potential during non-access periods' [patent_app_type] => B1 [patent_app_number] => 09/378548 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 8561 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477606.pdf [firstpage_image] =>[orig_patent_app_number] => 09378548 [rel_patent_id] =>[rel_patent_doc_number] =>)