Search

Sun J. Lin

Examiner (ID: 2153, Phone: (571)272-1899 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2825, 2851
Total Applications
1569
Issued Applications
1454
Pending Applications
15
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10741323 [patent_doc_number] => 20160087474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'Apparatus, System and Method for Charging a Mobile Device' [patent_app_type] => utility [patent_app_number] => 14/835997 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3774 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835997 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835997
Apparatus, System and Method for Charging a Mobile Device Aug 25, 2015 Abandoned
Array ( [id] => 11645690 [patent_doc_number] => 09667091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Battery pack with wireless charging and near field communication functions' [patent_app_type] => utility [patent_app_number] => 14/836926 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9032 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836926 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836926
Battery pack with wireless charging and near field communication functions Aug 25, 2015 Issued
Array ( [id] => 10713578 [patent_doc_number] => 20160059725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'METHOD AND APPARATUS FOR DETECTING CHARGER AND METHOD OF OPERATING THE CHARGER' [patent_app_type] => utility [patent_app_number] => 14/836337 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/836337
Method and apparatus for detecting charger and method of operating the charger Aug 25, 2015 Issued
Array ( [id] => 11898691 [patent_doc_number] => 09768638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'Method for charging one or more electronic devices and charging device therefor' [patent_app_type] => utility [patent_app_number] => 14/835288 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 13066 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835288 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835288
Method for charging one or more electronic devices and charging device therefor Aug 24, 2015 Issued
Array ( [id] => 10713575 [patent_doc_number] => 20160059722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'ELECTRIC POWER SUPPLY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/835037 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3377 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835037 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835037
Electric power supply device Aug 24, 2015 Issued
Array ( [id] => 12166983 [patent_doc_number] => 09885750 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-06 [patent_title] => 'Speed model tuning for programmable integrated circuits with consideration of device yield, simulated frequency of operation, and speed of device components' [patent_app_type] => utility [patent_app_number] => 14/750049 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750049 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750049
Speed model tuning for programmable integrated circuits with consideration of device yield, simulated frequency of operation, and speed of device components Jun 24, 2015 Issued
Array ( [id] => 11314356 [patent_doc_number] => 20160350466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'METHOD AND SYSTEM FOR TEMPLATE PATTERN OPTIMIZATION FOR DSA PATTERNING USING GRAPHOEPITAXY' [patent_app_type] => utility [patent_app_number] => 14/750742 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5881 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750742 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750742
Method and system for template pattern optimization for DSA patterning using graphoepitaxy Jun 24, 2015 Issued
Array ( [id] => 12759685 [patent_doc_number] => 20180145063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => INTEGRATED CIRCUIT LAYOUT USING LIBRARY CELLS WITH ALTERNATING CONDUCTIVE LINES [patent_app_type] => utility [patent_app_number] => 15/574813 [patent_app_country] => US [patent_app_date] => 2015-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/574813
Integrated circuit layout using library cells with alternating conductive lines Jun 23, 2015 Issued
Array ( [id] => 14801013 [patent_doc_number] => 10403516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Etching characteristic estimation method, program, information processing apparatus, processing apparatus, designing method, and production method [patent_app_type] => utility [patent_app_number] => 15/327731 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12009 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15327731 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/327731
Etching characteristic estimation method, program, information processing apparatus, processing apparatus, designing method, and production method Jun 14, 2015 Issued
Array ( [id] => 11523722 [patent_doc_number] => 09607125 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-28 [patent_title] => 'Context-aware reliability checks' [patent_app_type] => utility [patent_app_number] => 14/732971 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732971 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732971
Context-aware reliability checks Jun 7, 2015 Issued
Array ( [id] => 11345553 [patent_doc_number] => 09529962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-27 [patent_title] => 'System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design' [patent_app_type] => utility [patent_app_number] => 14/732160 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732160 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732160
System and method for generating and using sibling nets model for shared delay calculation across multi-instantiated blocks in the circuit design Jun 4, 2015 Issued
Array ( [id] => 11299899 [patent_doc_number] => 09507907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Computational wafer inspection' [patent_app_type] => utility [patent_app_number] => 14/730993 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730993 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730993
Computational wafer inspection Jun 3, 2015 Issued
Array ( [id] => 11333120 [patent_doc_number] => 09524366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-20 [patent_title] => 'Annotations to identify objects in design generated by high level synthesis (HLS)' [patent_app_type] => utility [patent_app_number] => 14/731300 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 10461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731300 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731300
Annotations to identify objects in design generated by high level synthesis (HLS) Jun 3, 2015 Issued
Array ( [id] => 13291217 [patent_doc_number] => 10156796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Method for determining the parameters of an IC manufacturing process by a differential procedure [patent_app_type] => utility [patent_app_number] => 15/310731 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6677 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15310731 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/310731
Method for determining the parameters of an IC manufacturing process by a differential procedure Jun 2, 2015 Issued
Array ( [id] => 11314335 [patent_doc_number] => 20160350446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'LINEAR ARRAY HIERARCHY NAVIGATION' [patent_app_type] => utility [patent_app_number] => 14/727497 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9114 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14727497 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/727497
Linear array hierarchy navigation May 31, 2015 Issued
Array ( [id] => 11314353 [patent_doc_number] => 20160350463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'Circuit Modeling With Partitioned Input Ranges' [patent_app_type] => utility [patent_app_number] => 14/726571 [patent_app_country] => US [patent_app_date] => 2015-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4828 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726571 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726571
Circuit Modeling With Partitioned Input Ranges May 30, 2015 Abandoned
Array ( [id] => 11598959 [patent_doc_number] => 09646129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Notch detection and correction in mask design data' [patent_app_type] => utility [patent_app_number] => 14/726304 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 35 [patent_no_of_words] => 7644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726304 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726304
Notch detection and correction in mask design data May 28, 2015 Issued
Array ( [id] => 11411005 [patent_doc_number] => 09558310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Method and system for template pattern optimization for DSA patterning using graphoepitaxy' [patent_app_type] => utility [patent_app_number] => 14/723570 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5844 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723570 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723570
Method and system for template pattern optimization for DSA patterning using graphoepitaxy May 27, 2015 Issued
Array ( [id] => 10461741 [patent_doc_number] => 20150346756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/724619 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14724619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/724619
Semiconductor device May 27, 2015 Issued
Array ( [id] => 11095370 [patent_doc_number] => 20160292339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SEMICONDUCTOR DEVICE AND LAYLOUT METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/722714 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14722714 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/722714
Semiconductor device and layout method thereof May 26, 2015 Issued
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